Nanostructure-FET Gate Structures for Gate Dielectric Protection
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, challenges arise in maintaining the integrity and performance of transistor structures, particularly in nanostructure-FETs, due to issues such as damage to gate dielectric layers during processing.
Innovation Solution
A protection layer is applied to the work function tuning layer during annealing to prevent damage, followed by an oxygen-containing etchant to form a dielectric barrier layer, which remains intact, enhancing the stability and performance of the gate electrode layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but the integrity and performance of transistor structures become more difficult to maintain
Solution Approach 1:
A protection layer is formed over the work function tuning layer before the annealing process. This preliminary protective measure prevents damage to the work function tuning layer during subsequent processing steps, allowing minimum feature sizes to be reduced while maintaining transistor structure integrity and performance.
2Reliability
If processing steps are performed to improve device performance, then transistor functionality is enhanced, but damage to the gate dielectric layer occurs
Solution Approach 1:
A protection layer is introduced as an intermediary between the work function tuning layer and the annealing process. This intermediate protective layer absorbs the harmful effects of the annealing process, preventing direct damage to the gate dielectric layer while still allowing the annealing process to improve device performance.
Solution Approach 2:
The protection layer is removed using an oxygen-containing etchant, which simultaneously forms a dielectric barrier layer on the work function tuning layer. This converts the potentially harmful etching process into a beneficial action that creates an additional protective barrier, preventing damage to the gate dielectric layer during subsequent processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach helps maintain the integrity of the gate dielectric layer, improving the performance of p-type devices by preventing damage during subsequent processing steps.
Implementation Method 1
The protection layer is removed with an oxygen-containing etchant, which promotes formation of a dielectric barrier layer on the work function tuning layer
Implementation Method 2
The protection layer is removed with an oxygen-containing etchant, which promotes formation of a dielectric barrier layer on the work function tuning layer
Implementation Method 3
An annealing process is subsequently performed to modify the work function of an underlying gate dielectric layer
Data Source
AI summary
In an embodiment, a device includes: a first nanostructure; a gate dielectric layer around the first nanostructure; a first p-type work function tuning layer on the gate dielectric layer; a dielectric barrier layer on the first p-type work function tuning layer; and a second p-type work function tuning layer on the dielectric barrier layer, the dielectric barrier layer being thinner than the first p-type work function tuning layer and the second p-type work function tuning layer.