Nanostructure FET Gate Segmentation for Channel Stress Relief
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, challenges arise in maintaining integration density and reducing stress on channel regions, leading to deformation and reduced carrier mobility, which affects the performance of field-effect transistors.
Innovation Solution
A Cut Metal Gate (CMG) process is used to form dielectric plugs, followed by a Continuous Metal On-Diffusion Edge (CMODE) process to replace a dummy gate structure, minimizing deformation and stress on the channel regions, thereby improving carrier mobility and tolerance to pattern inaccuracies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature size is reduced to improve integration density, then more components can be integrated into a given area, but stress on channel regions increases causing deformation and reduced carrier mobility
Solution Approach 1:
The gate structure is segmented into multiple sections with dielectric plugs positioned between them, allowing independent stress management for each transistor channel region. This segmentation enables localized stress relief without affecting adjacent channels, maintaining high integration density while improving carrier mobility in each individual channel.
Solution Approach 2:
Dielectric plugs are introduced as intermediary structures between gate sections, positioned to provide mechanical support and stress relief to channel regions. These plugs act as mediators that prevent deformation of the channel while maintaining the compact layout required for high integration density.
2Adaptability or versatility
If conventional gate structure replacement is used to improve manufacturing flexibility, then process adaptability increases, but deformation and stress on channel regions occurs reducing carrier mobility
Solution Approach 1:
Dielectric plugs are formed in the gate structure before the gate material is deposited and patterned. This preliminary action ensures that the structural support is in place before subsequent processing steps, preventing channel region deformation during manufacturing while maintaining flexibility in gate material selection and processing methods.
Solution Approach 2:
The dielectric plugs are positioned to preemptively counteract the stress and deformation that would occur during gate structure formation and subsequent processing. By establishing this protective structure in advance, the method prevents channel distortion while allowing various manufacturing approaches.
3Area of stationary object
If gate structure is made more compact to improve integration density, then device size is reduced, but stress concentration increases causing channel deformation
Solution Approach 1:
The compact gate structure is divided into discrete sections separated by dielectric plugs, which segment the stress distribution. This allows the overall device area to remain small while preventing stress concentration in any single channel region, as each segment is independently supported.
Solution Approach 2:
Dielectric plugs are strategically positioned at specific locations within the compact gate structure where stress concentration would occur. This local reinforcement provides targeted stress relief exactly where needed, maintaining compact dimensions while preventing channel deformation at critical points.
Data Source
AI summary
A method of forming a semiconductor device includes: forming a dummy gate structure over a first fin and around first channel regions that are disposed over the first fin; forming an interlayer dielectric (ILD) layer over the first fin around the dummy gate structure; replacing the dummy gate structure with a gate structure; forming a first dielectric plug and a second dielectric plug in the gate structure on opposing sides of the first fin, where the first and second dielectric plugs cut the gate structure into a plurality of segments separated from each other; removing a segment of the gate structure interposed between the first dielectric plug and the second dielectric plug to expose the first channel regions; removing the exposed first channel regions, where after removing the exposed first channel regions, a recess is formed in the ILD layer; and filling the recess with a dielectric material.