Nanostructure FET Isolation Structure for Source-Drain Leakage
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, they face challenges such as increased leakage current between source/drain regions, which affects device performance and power consumption, due to the difficulty in effectively isolating these regions from the underlying fins.
Innovation Solution
The formation of isolation structures under the source/drain regions using a U-shaped liner material with a dielectric layer comprising silicon nitride, which includes multiple sublayers with varying atomic ratios of nitrogen to silicon, allowing for tuning of properties like dielectric constant and etch rate to enhance electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature size is reduced to increase integration density, then more components can be integrated into a given area, but leakage current between source/drain regions increases
Solution Approach 1:
The isolation structure is divided into multiple sublayers (first sublayer, second sublayer, third sublayer) with different dielectric constants. This segmentation allows each layer to contribute differently to the overall isolation performance, enabling effective leakage current blocking while maintaining compact dimensions for high integration density.
Solution Approach 2:
The isolation structure uses a composite dielectric material system with layers of different dielectric constants (first dielectric constant, second dielectric constant, third dielectric constant). This composite approach creates a multi-barrier isolation structure that effectively prevents leakage current between source/drain regions in scaled devices.
2Object-generated harmful factors
If isolation structures are made more robust to reduce leakage current, then electrical isolation improves, but device complexity increases
Solution Approach 1:
The invention varies the dielectric constant parameter across different isolation layers (first dielectric constant, second dielectric constant, third dielectric constant) to optimize isolation performance. By adjusting these material parameters rather than increasing structural complexity, effective leakage current reduction is achieved with manageable device complexity.
3Reliability
If feature size is reduced to improve device performance, then switching speed and efficiency improve, but power consumption increases due to leakage current
Solution Approach 1:
The multi-sublayer isolation structure segments the electrical isolation function into multiple specialized layers. This segmentation effectively blocks leakage current paths that would otherwise increase power consumption in scaled devices, enabling high-performance operation with reduced energy loss.
Solution Approach 2:
The composite dielectric structure with varying dielectric constants creates multiple electrical barriers that prevent leakage current. This reduces unwanted current flow and associated power consumption while allowing the device to maintain high performance through continued scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces leakage current, improves device performance, and decreases power consumption by creating a robust electrical isolation between source/drain regions and the underlying fins, while being integratable into existing manufacturing flows.
Implementation Method 1
isolation structures under the source/drain regions, wherein the isolation structures separate the source/drain regions from the fin
Data Source
AI summary
A semiconductor device includes: a substrate; a fin protruding above the substrate; a gate structure over the fin; source/drain regions over the fin and on opposing sides of the gate structure; channel layers over the fin and between the source/drain regions, where the gate structure wraps around the channel layers; and isolation structures under the source/drain regions, where the isolation structures separate the source/drain regions from the fin, where each of the isolation structures includes a liner layer and a dielectric layer over the liner layer, where the dielectric layer has a plurality of sublayers.