Nanostructure FET Mark Structure for Selective Etch Protection

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

As semiconductor devices continue to shrink in size, challenges arise in the fabrication process that affect the integration density and reliability of electronic components, particularly due to issues with etch damage and selectivity in removing material layers.

Innovation Solution

The use of oxide dummy regions between channel regions in nanostructure-FETs allows for more selective etching, reducing the risk of damage to the channel and source/drain regions, and the incorporation of mark structures that include portions of these oxide dummies for improved manufacturing precision.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional etching processes are used to remove material layers, then manufacturing efficiency is maintained, but etch damage occurs to channel and source/drain regions

Engineering Contradiction:
Improvedamage to channel and source/drain regionsVSAvoidmanufacturing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

An oxide dummy region is introduced as an intermediary layer between the channel region and the material to be removed. This dummy region acts as a sacrificial buffer that absorbs etch damage, protecting the channel and source/drain regions from direct etch exposure while allowing the etching process to proceed with high selectivity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The oxide dummy region is formed in advance before the etching process. This preliminary structure preparation ensures that protective measures are already in place before the harmful etching action begins, preventing etch damage to critical regions while maintaining manufacturing efficiency.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If material layers are removed with high selectivity to protect channel regions, then reliability improves, but additional process steps are required

Engineering Contradiction:
Improveselectivity of material removalVSAvoidprocess steps
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The oxide dummy region serves multiple functions simultaneously: it acts as a protective buffer during etching, provides a reference structure for mark formation, and enables selective removal processes. By merging these functions into a single structural element, the patent achieves high selectivity without proportionally increasing process complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The oxide dummy region is designed to perform multiple roles in the fabrication process: protecting channel regions during etching, serving as a template for mark structure formation, and enabling selective material removal. This multi-functionality reduces the need for separate dedicated structures for each purpose.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If integration density is increased by reducing feature size, then productivity improves, but etch damage and selectivity issues worsen

Engineering Contradiction:
Improveintegration densityVSAvoidetch damage and selectivity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The oxide dummy region is strategically positioned only where needed - between channel regions and adjacent to areas requiring selective etching. This localized placement provides targeted protection to critical nanoscale features without affecting other parts of the device, enabling high integration density while maintaining reliability through selective etching processes.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20250372530A1Mark structure for nanostructure device and methods of forming the same
Publication Date: 2025.12.04 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250372530A1 patent drawing
  • US20250372530A1 patent drawing
  • US20250372530A1 patent drawing

AI summary

A method includes forming a first nanostructure stack and a second nanostructure stack over a substrate, wherein the first nanostructure stack and the second nanostructure stack include alternating layers of a first semiconductor material and a second semiconductor material; performing a first etching process, wherein the first etching process removes the first semiconductor material of the first nanostructure stack to form first openings and recesses the first semiconductor material of the second nanostructure stack to form second openings; depositing a first dielectric material in the first openings and on the second semiconductor material in the second openings; performing a second etching process, wherein the second etching process removes the first dielectric material from the first openings, wherein the first dielectric material remains on the second semiconductor material in the second openings after performing the second etching process; and forming gate structures in the first openings.