Nanostructure-FET Source/Drain Regions for Strain and Diffusion Control
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, challenges arise from impurity diffusion and reduced performance due to strain limitations in channel regions, which affect the integration density and efficiency of electronic components.
Innovation Solution
The introduction of strain layers composed of semiconductor materials, such as germanium, over the sidewalls of channel regions in nanostructure-FETs to enhance tensile strain and reduce impurity diffusion, thereby improving performance and integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature size is reduced to improve integration density, then more components can be integrated into a given area, but impurity diffusion and strain limitations arise that reduce device performance
Solution Approach 1:
The patent applies local quality by forming strain layers with specific material composition (e.g., silicon germanium with varying germanium content) in specific locations (source/drain regions adjacent to channel regions) to provide localized tensile strain where needed most, while maintaining different material properties in other regions of the device
Solution Approach 2:
The patent uses composite materials by combining silicon with germanium to form silicon germanium alloy layers, where the germanium content can be varied (e.g., 5-50% Ge) to create materials with tailored mechanical and electrical properties that simultaneously address strain requirements and impurity diffusion barriers
2Productivity
If channel region size is reduced to enable smaller transistors, then integration density increases, but tensile strain in the channel region decreases leading to reduced carrier mobility
Solution Approach 1:
The patent applies the counterweight principle by introducing strain layers that exert tensile stress on the channel region, counteracting the compressive effects and reduced strain that result from scaling down the channel dimensions, thereby maintaining carrier mobility despite smaller feature sizes
Solution Approach 2:
The patent changes physical parameters by modifying the material composition (germanium content), layer thickness (e.g., 1-10 nm), and stress state of the strain layers to optimize tensile strain in the channel region while accommodating reduced channel dimensions for higher integration density
3Productivity
If source/drain regions are scaled down to match smaller feature sizes, then integration density improves, but impurity diffusion becomes more significant relative to the smaller dimensions
Solution Approach 1:
The patent introduces strain layers as intermediary structures between the source/drain regions and channel regions, which serve as diffusion barriers to prevent impurity migration while also providing the necessary mechanical strain to the channel, thus addressing both integration density and impurity control requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The strain layers increase the tensile strain of channel regions, enhancing the performance of n-type nanostructure-FETs and reducing undesirable process issues caused by impurity diffusion, leading to improved integration density and device efficiency.
Implementation Method 1
The strain layers can increase the tensile strain of the channel regions, which can improve performance of the n-type nanostructure-FETs
Implementation Method 2
The strain layers can reduce the diffusion of impurities into the channel regions during manufacturing
Data Source
AI summary
A device includes a stack of first nanostructures; a first insulating layer adjacent to the stack of first nanostructures; and a first source/drain region over the first insulating layer, wherein the first source/drain region includes: first semiconductor layers, wherein each first semiconductor layer covers a sidewall of a respective first nanostructure, wherein the first semiconductor layers includes a first semiconductor material; second semiconductor layers, wherein each second semiconductor layer covers a sidewall of a respective first semiconductor layer, wherein the second semiconductor layers includes a second semiconductor material different from the first semiconductor material; and a third semiconductor layer on the second semiconductor layer, wherein the third semiconductor layer is a third semiconductor material different from the first semiconductor material and different from the second semiconductor material.