GAA Nanostructure Gate Layout With Air Spacer Isolation
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Solution Overview
Problem
Conventional methods for manufacturing gate-all-around (GAA) devices face challenges as they scale down, leading to increased parasitic capacitance, which decreases performance.
Innovation Solution
The introduction of voids between the gate structure and the contact etch stop layer serves as gate spacers to decrease parasitic capacitance, utilizing methods such as double-patterning or multi-patterning processes to create GAA transistor structures with improved gate control and reduced leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional manufacturing methods are used for GAA devices, then manufacturing process is simpler, but parasitic capacitance increases and performance decreases
Solution Approach 1:
The patent extracts the harmful dielectric material between the gate structure and contact etch stop layer, replacing it with voids (air gaps). This removal of the harmful dielectric material directly reduces parasitic capacitance between the gate and contact etch stop layer, improving device performance while eliminating the harmful electrical coupling.
Solution Approach 2:
The patent introduces voids (air gaps) as a porous/empty space structure between the gate structure and contact etch stop layer. These voids act as low-k dielectric regions with effectively zero dielectric constant, minimizing parasitic capacitance while maintaining structural integrity through the seal layer.
2Area of moving object
If GAA devices are scaled down, then chip footprint is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary patterning actions using double-patterning or multi-patterning processes to pre-establish the complex gate-all-around structure before final device formation. This preliminary structuring simplifies subsequent manufacturing steps while achieving the required small footprint and complex geometry.
Solution Approach 2:
The patent transitions from two-dimensional planar transistors to three-dimensional gate-all-around structures, wrapping the gate around the channel in multiple dimensions. This vertical and lateral dimensionality enables superior gate control and scaling to smaller footprints while the systematic formation process manages the manufacturing complexity.
3Reliability
If gate spacers are introduced to reduce parasitic capacitance, then device performance improves, but structural complexity increases
Solution Approach 1:
The patent introduces a seal layer as an intermediary structure that defines and contains the voids between the gate structure and contact etch stop layer. This seal layer acts as a mediator that provides structural support while enabling the low-capacitance void region, improving gate control without excessive complexity.
Solution Approach 2:
The patent creates a composite structure combining the gate structure, voids (air gaps), seal layer, and contact etch stop layer. This multi-material composite architecture optimizes electrical performance by combining conductive, insulating, and structural materials in a integrated design that reduces parasitic capacitance while maintaining manufacturability.
Data Source
AI summary
A semiconductor structure includes a substrate and nanostructures over the substrate. The semiconductor structure also includes a gate structure wrapping around the nanostructures. The gate structure comprises a gate dielectric layer and a gate electrode wrapping around the gate dielectric layer. The semiconductor structure further includes a source/drain feature in contact with the nanostructures. In addition, the semiconductor structure includes a contact etch stop layer over the source/drain feature. The contact etch stop layer is separated from the gate structure by an air spacer. The semiconductor structure also includes a seal layer over the air spacer and the gate structure, on a sidewall of the contact etch stop layer, and on a top surface of the nanostructures. A portion of the seal layer is below the air spacer.