Nanostructure Gate Dielectric Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
The challenge in semiconductor manufacturing is the increasing complexity and parasitic capacitance in nanostructure transistors due to the scaling down process, which affects device performance and reliability.
Innovation Solution
The implementation of a gate-protection top (GPT) hard mask to selectively remove high-k dielectric material from low-k dielectric spacers, combined with thicker low-k dielectric spacers to reduce parasitic capacitance and improve device performance by increasing the distance between source/drain contacts and gate contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the geometry size is decreased through scaling down process, then functional density increases, but parasitic capacitance increases and device complexity increases
Solution Approach 1:
The patent extracts and removes the high-k dielectric material from the gate spacer structure using a gate-protection top hard mask. This selective removal reduces the parasitic capacitance between the gate and source/drain regions while preserving the high functional density achieved through scaling, directly addressing the harmful effect of increased parasitic capacitance.
Solution Approach 2:
The patent applies different dielectric materials (high-k and low-k) in different locations of the gate structure. The high-k dielectric is removed from the gate spacer region to reduce parasitic capacitance, while the low-k dielectric remains in the channel region to maintain gate control. This local differentiation resolves the contradiction by optimizing each region for its specific function.
2Reliability
If high-k dielectric material is used in gate spacer, then gate control is improved, but parasitic capacitance increases
Solution Approach 1:
The patent selectively extracts the high-k dielectric material from the gate spacer using a gate-protection top hard mask that protects the channel region while allowing removal from the spacer region. This extraction reduces parasitic capacitance while maintaining gate control through the remaining low-k dielectric in the channel area.
Solution Approach 2:
The patent segments the gate dielectric structure into different regions: the gate spacer region where high-k dielectric is removed to reduce parasitic capacitance, and the gate channel region where low-k dielectric remains to maintain gate control. This segmentation allows each region to be optimized independently for its specific function.
3Object-generated harmful factors
If low-k dielectric spacers are made thicker to reduce parasitic capacitance, then device performance improves, but manufacturing complexity increases
Solution Approach 1:
The patent forms the gate-protection top hard mask before the selective removal process. This preliminary action defines the precise region from which high-k dielectric will be removed, enabling the thickening of low-k dielectric spacers to proceed with controlled manufacturing complexity rather than requiring complex post-processing adjustments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic capacitance while maintaining beneficial on-current (ION) in nanostructure FETs, enhancing device reliability and performance by minimizing electrical interference.
Implementation Method 1
selectively removing portions of the gate dielectric that are outside the channels and the inner spacers from the gate spacer
Data Source
AI summary
A semiconductor device includes a stack of nanostructures, a first layer over and offset from the stack of nanostructures, an inner spacer between the first layer and the stack of nanostructures, and a gate structure wrapping around the stack of nanostructures. The gate structure includes a gate dielectric on the nanostructures and between the inner spacer and the nanostructures of the stack of nanostructures and a gate metal on the gate dielectric.