Wrap-Around Nanostructure Gate Layout for Tighter Dummy Gate Pitch
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Solution Overview
Problem
Existing semiconductor device fabrication processes face challenges in achieving high device density and performance while maintaining low costs, particularly in forming three-dimensional designs where issues such as dummy gate electrode layer collapse and reduced pitch between gate structures hinder efficiency.
Innovation Solution
The proposed solution involves forming a semiconductor device structure with nanostructures over a substrate, where a gate spacer layer is formed before the dummy gate electrode layer, reducing the aspect ratio and minimizing the risk of collapse. This approach allows for a reduced pitch between adjacent dummy gate structures, enhancing device density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the dummy gate electrode layer is formed before the gate spacer layer, then the fabrication process follows conventional sequencing, but the aspect ratio increases and collapse risk increases
Solution Approach 1:
The gate spacer layer is formed in advance before the dummy gate electrode layer, creating a supportive structure that prevents collapse during subsequent fabrication steps. This preliminary action of building the spacer framework first enables the dummy gate to be formed with reduced aspect ratio and improved structural stability.
2Productivity
If the pitch between gate structures is reduced to increase device density, then more devices can be integrated, but the risk of structural collapse increases
Solution Approach 1:
By forming the gate spacer layer before the dummy gate electrode layer, a supportive framework is established that enables tighter pitch between gate structures. The pre-formed spacer provides structural reinforcement that allows reduced spacing without increasing collapse risk, thereby enabling higher device density.
Solution Approach 2:
The invention changes the fabrication sequence parameter, forming the gate spacer layer at an earlier stage rather than after the dummy gate electrode layer. This parameter change in process sequencing fundamentally alters the structural development pathway, enabling reduced pitch while maintaining stability.
3Reliability
If the aspect ratio of the dummy gate electrode layer is reduced to prevent collapse, then structural stability improves, but the pitch between gate structures must be increased
Solution Approach 1:
The gate spacer layer is formed first to create a supportive framework that enables the dummy gate electrode layer to achieve reduced aspect ratio without requiring increased pitch. The preliminary spacer structure provides the necessary support to maintain stability at tighter spacings, thereby preventing the trade-off between stability and density.
Data Source
AI summary
A semiconductor device structure is provided. The semiconductor device structure includes a plurality of first nanostructures stacked over a substrate in a vertical direction. The semiconductor device structure includes a first gate structure surrounding the first nanostructures. The semiconductor device structure also includes a first gate spacer layer formed adjacent to the first gate structure. A topmost first nanostructure has a first portion directly below the gate spacer layer and a second portion directly below the first gate structure, and the first portion has a first height along the vertical direction, the second portion has a second height along the vertical direction, and the first height is greater than the second height.