Nanostructure Gate Footing Profile to Prevent Residue and Voids
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, the integration density of electronic components increases, but this miniaturization introduces challenges such as reduced processing windows and potential damage during replacement gate processes and epitaxial growth, particularly due to the footprint of dummy gates in nanostructure transistors.
Innovation Solution
Forming dummy gates with a small footing profile around semiconductor fins and nanostructures, which allows for increased processing windows during subsequent operations like replacement gate processes and epitaxial growth by facilitating easier removal and reducing residue, thereby enhancing manufacturing yield and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dummy gates are formed with a conventional footing profile, then the gate structure provides adequate coverage, but residue forms beneath epitaxial source/drain regions and voids form in replacement gates
Solution Approach 1:
The dummy gate structure implements local quality by creating different footing profiles at different locations. The portion of the dummy gate beneath the channel region has a first footing profile that extends further laterally, while the portion beneath the source/drain regions has a second footing profile that extends less laterally. This localized differentiation prevents residue formation and voids while maintaining adequate gate coverage where needed.
Solution Approach 2:
The invention inverts the conventional approach by designing the dummy gate footing profile to be non-uniform rather than uniform. Instead of extending the dummy gate uniformly beneath all regions, the footprint is reduced beneath the source/drain regions while maintaining or enhancing coverage beneath the channel region. This inverted approach eliminates the harmful effects of uniform extension while preserving beneficial coverage.
2Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but processing windows are reduced and damage occurs during replacement gate processes and epitaxial growth
Solution Approach 1:
The dummy gate structure implements local quality by creating different footing profiles at different locations. The portion of the dummy gate beneath the channel region has a first footing profile that extends further laterally, while the portion beneath the source/drain regions has a second footing profile that extends less laterally. This localized differentiation prevents residue formation and voids while maintaining adequate gate coverage where needed.
Solution Approach 2:
The invention inverts the conventional approach by designing the dummy gate footing profile to be non-uniform rather than uniform. Instead of extending the dummy gate uniformly beneath all regions, the footprint is reduced beneath the source/drain regions while maintaining or enhancing coverage beneath the channel region. This inverted approach eliminates the harmful effects of uniform extension while preserving beneficial coverage.
Data Source
AI summary
In an embodiment, a device includes: an isolation region; nanostructures protruding above a top surface of the isolation region; a gate structure wrapped around the nanostructures, the gate structure having a bottom surface contacting the isolation region, the bottom surface of the gate structure extending away from the nanostructures a first distance, the gate structure having a sidewall disposed a second distance from the nanostructures, the first distance less than or equal to the second distance; and a hybrid fin on the sidewall of the gate structure.