Semiconductor Nanostructure Gate Wrapping With Selective Layer Trimming
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Solution Overview
Problem
The challenge in semiconductor manufacturing is forming reliable semiconductor devices as feature sizes continue to decrease, making fabrication processes increasingly complex and difficult.
Innovation Solution
The process involves forming a semiconductor stack with alternating sacrificial and semiconductor layers, patterning fin structures, forming dummy gate stacks and gate spacers, removing sacrificial layers, and wrapping metal gate stacks around the semiconductor nanostructures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency and cost are improved, but fabrication process complexity and difficulty increase
Solution Approach 1:
The fabrication process is divided into multiple patterning steps (first pattern forming, second pattern forming) with intermediate etching and trimming operations. This segmentation allows complex nanostructures to be built through manageable sequential steps rather than attempting to create all features in a single process, thereby managing fabrication complexity while achieving high functional density
Solution Approach 2:
Sacrificial layers are formed and positioned in advance before the final semiconductor nanostructures are created. These preliminary structures guide subsequent patterning and etching steps, enabling precise formation of complex devices through pre-planned process sequences that reduce overall fabrication difficulty
2Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency and cost are improved, but manufacturing reliability deteriorates
Solution Approach 1:
Different regions of the semiconductor structure receive different treatments through selective etching and trimming operations. Edge portions of semiconductor layers are preserved with full thickness while intermediate portions are trimmed to reduced thickness, creating local variations that optimize both device performance and reliability in different areas of the structure
Solution Approach 2:
Multiple process steps including pattern formation, etching, trimming, and sacrificial layer removal are performed in advance to ensure proper structure formation before final device assembly. This preliminary structuring with built-in process margins and verification steps cushions against variability and ensures reliable device operation at scaled dimensions
3Stability of the object's composition
If alternating sacrificial and semiconductor layers are formed to create nanostructures, then structural integrity is improved, but device complexity increases
Solution Approach 1:
Sacrificial layers are selectively removed from the alternating layer structure through targeted etching processes. This extraction of specific layers transforms the complex multi-layer structure into the desired semiconductor nanostructure configuration, maintaining structural integrity by preserving the semiconductor layers while eliminating the sacrificial material that enabled the structure's formation
4Reliability
If metal gate stacks are wrapped around semiconductor nanostructures, then device performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The gate structure is formed by wrapping metal gate stacks around the semiconductor nanostructures in a three-dimensional configuration rather than placing gates only on top surfaces. This dimensional transition from planar to wrapped gates improves device performance by enhancing gate control, while the self-aligned nature of the wrapping process helps manage the increased manufacturing precision requirements
Data Source
AI summary
A semiconductor device structure and a formation method are provided. The method includes forming a fin structure over a substrate, and the fin structure has multiple sacrificial layers and multiple semiconductor layers laid out in an alternating manner. The method also includes forming a dummy gate stack extending across a portion of the fin structure and forming gate spacers over sidewalls of the dummy gate stack. The gate spacers extend across portions of the fin structure. The method further includes removing the dummy gate stack to form a trench exposing the portion of the fin structure and trimming the semiconductor layers exposed by the trench. Each of the semiconductor layers covered by the gate spacers becomes wider than each of the semiconductor layers that is trimmed. In addition, the method includes removing the sacrificial layers and forming a metal gate stack wrapped around the semiconductor layers.