Nanostructure Gate Metal Selectivity for PMOS Threshold Control
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Solution Overview
Problem
As semiconductor devices shrink in size, transistors face issues such as short channel effects, hot carrier degradation, barrier lowering, and increased source/drain electron tunneling, leading to off-current and power efficiency degradation, which silicon germanium nanostructure transistors aim to mitigate.
Innovation Solution
The formation of gate structures that wrap around nanostructure channels, combined with specific metal choices for PMOS and NMOS transistors, uses a self-assembled monolayer to prevent n-type gate metal deposition on p-type gate metal, optimizing threshold voltages and reducing current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate length is reduced for smaller technology nodes, then transistor size decreases and integration density increases, but source/drain electron tunneling increases leading to higher off current
Solution Approach 1:
The channel is segmented into multiple nanoscale channels (nanowires, nanosheets) arranged in series, creating multiple barriers for electron transport. This segmentation increases the effective barrier height and reduces off-state tunneling current while maintaining small footprint for high integration density
Solution Approach 2:
The invention transitions from planar 2D channels to vertically stacked 3D nanostructure channels (nanowires, nanosheets). This dimensional change enables gate-all-around control and increases the effective channel area without increasing planar footprint, reducing off-current through enhanced electrostatic control
2Reliability
If silicon germanium nanostructure transistors are used, then short channel effects and carrier mobility are improved, but device complexity increases
Solution Approach 1:
Multiple nanoscale channels are nested vertically to form stacked structures (nanowire bundles, nanosheet stacks). The gate structure wraps around each channel in a nested configuration, providing gate-all-around control. This nesting achieves superior SCE control and high drive current while maintaining compact footprints
Solution Approach 2:
The invention uses composite material structures combining silicon channels with silicon germanium sacrificial layers and gate dielectric materials. The selective etching of SiGe layers releases and suspends silicon nanowire/nanosheet channels, creating complex 3D structures with enhanced electrostatic control and carrier mobility
3Manufacturing precision
If self-assembled monolayer is used to prevent n-type gate metal deposition on p-type gate metal, then threshold voltage control is improved, but manufacturing process complexity increases
Solution Approach 1:
A self-assembled monolayer is introduced as an intermediary between the p-type gate metal and the deposition environment. This monolayer selectively prevents n-type gate metal deposition on p-type gate structures while allowing deposition on n-type gate structures, enabling precise threshold voltage control through selective metal layer formation
Solution Approach 2:
The invention changes the surface chemistry parameters of the gate metal by applying self-assembled monolayers with specific functional groups. This parameter change creates selective surface properties that control metal deposition behavior, enabling differential deposition of n-type and p-type gate metals on different gate structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances control over the gate structure, increases drive current, reduces short channel effects, and achieves high operating efficiency for both PMOS and NMOS transistors, enabling low current leakage and optimal power efficiency.
Implementation Method 1
forming a self-assembled monolayer on the first type gate metal
Implementation Method 2
the self-assembled monolayer prevents n-type gate metal deposition on the first type gate metal
Data Source
AI summary
Some implementations described herein provide semiconductor manufacturing techniques and associated semiconductor structures for forming p-type metal-oxide-semiconductor (PMOS) nanostructure transistors and n-type metal-oxide-semiconductor (NMOS) nanostructure transistors in a semiconductor device. The techniques described herein include forming respective (different) types of gate metals for a PMOS nanostructure transistor and keeping an intrinsic NMOS nanostructure transistor of the semiconductor device. A p-type gate metal may be formed around nanostructure channels for the PMOS nanostructure transistor. A self-assembled monolayer may then be formed on the surface of the p-type gate metal layer. During formation of an n-type gate metal around the nanostructure channels for the NMOS nanostructure transistor, the self-assembled monolayer on the p-type gate metal resists formation of the n-type gate metal on the p-type gate metal. This results in little-to-no n-type gate metal deposition on the p-type gate metal, which minimizes the p-type threshold voltage (PV) impact to the PMOS nanostructure transistor.