Nanostructure Gate Metal Oxide Barrier for Threshold Voltage Balance
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Solution Overview
Problem
As semiconductor devices shrink in size, transistors face challenges such as short channel effects, increased source/drain electron tunneling, and threshold voltage imbalances between PMOS and NMOS nanostructure transistors, leading to inefficiencies and high current leakage.
Innovation Solution
The formation of p-type and n-type gate metals with a metal oxide layer on the p-type gate metal to resist n-type gate metal deposition, optimizing threshold voltages for both PMOS and NMOS nanostructure transistors, thereby minimizing current leakage and enhancing operating efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If gate length is reduced for smaller technology nodes, then transistor size decreases and integration density improves, but source/drain electron tunneling increases leading to higher off current
Solution Approach 1:
The gate structure is segmented into multiple materials with different work functions (p-type gate metal for PMOS regions, n-type gate metal for NMOS regions) to independently control threshold voltages in different transistor types, thereby reducing electron tunneling and off current in each region
Solution Approach 2:
Different gate metal materials are applied to different regions (PMOS vs NMOS) to provide locally optimized work functions and threshold voltages, addressing the specific needs of each transistor type to minimize harmful tunneling effects
2Ease of manufacture
If conventional gate metal deposition is used without selective resistance, then deposition process is simple, but n-type gate metal deposits on p-type gate metal causing threshold voltage imbalance
Solution Approach 1:
A metal oxide layer is introduced as an intermediary between the p-type gate metal and the deposition environment, serving as a selective barrier that prevents n-type gate metal from depositing on the p-type region while allowing the deposition process to remain relatively simple
Solution Approach 2:
The surface properties of the gate metal are changed by forming a metal oxide layer, which alters the deposition characteristics to achieve selective metal deposition based on the underlying gate metal type, thereby maintaining threshold voltage balance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves low current leakage and high operating efficiency for both PMOS and NMOS nanostructure transistors by tuning their work functions, reducing short channel effects and improving control over conductive channels.
Implementation Method 1
a metal oxide layer on the p-type gate metal to resist n-type gate metal deposition
Implementation Method 2
optimizing threshold voltages for both PMOS and NMOS nanostructure transistors by tuning their work functions
Implementation Method 3
improving control over conductive channels... minimizing current leakage
Data Source
AI summary
Techniques described herein include forming respective (different) types of gate metals for a p-type metal oxide semiconductor (PMOS) nanostructure transistor and keep intrinsic n-type metal oxide semiconductor (NMOS) nanostructure transistor of the semiconductor device. A p-type gate metal may be formed around nanostructure channels for the PMOS nanostructure transistor. The surface of the p-type gate metal may then be oxidized to form a metal oxide layer on the p-type gate metal. During formation of an n-type gate metal around the nanostructure channels for the NMOS nanostructure transistor, the metal oxide layer on the p-type gate metal resists formation of the n-type gate metal on the p-type gate metal. This results in little to no n-type gate metal deposition on the p-type gate metal, which minimizes the p-type threshold voltage (PVt) impact to the PMOS nanostructure transistor.