Nanostructure Gate Width Control Through Differential Spacer Etching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional fabrication techniques for nanostructure devices, such as GAA FETs, result in non-uniform gate widths due to variations in fin stack shapes, leading to suboptimal device performance.
Innovation Solution
By varying the characteristics of sacrificial semiconductor layers, such as germanium concentration or thickness, to control the etch rate during the patterning process, ensuring a uniform gate width is achieved through controlled lateral etching and deposition of dielectric spacers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication techniques are used for patterning fin stacks, then the manufacturing process is simple, but the gate width becomes non-uniform due to variations in fin stack shapes
Solution Approach 1:
The patent applies preliminary action by performing a first lateral etch on the sacrificial semiconductor layers before forming the gate structure. This pre-etching step creates a more uniform fin stack shape in advance, which then enables uniform gate width when the gate is formed later. The preliminary etching modifies the substrate geometry before the main gate fabrication process, resolving the uniformity issue without requiring complex real-time adjustments during gate formation.
Solution Approach 2:
The patent employs parameter changes by varying the etch rate across different layers of the sacrificial semiconductor structure. By controlling the etch rate parameters (through selective etching of layers with different germanium concentrations or thicknesses), the process achieves differential material removal that compensates for initial fin stack shape variations, resulting in uniform gate width despite the simplicity of the overall fabrication approach.
2Reliability
If the fin stack shape varies, then the device structure is formed, but the gate width becomes non-uniform leading to suboptimal device performance
Solution Approach 1:
The patent performs a preliminary lateral etch of the sacrificial semiconductor layers before gate formation. This advance modification of the fin stack geometry compensates for shape variations, ensuring that when the gate is subsequently formed, it achieves uniform width across the device. This preliminary action directly addresses the root cause of non-uniform gate width and the associated device performance issues.
Solution Approach 2:
The sacrificial semiconductor layers serve as an intermediary element that enables gate width uniformity. By selectively removing portions of these intermediate sacrificial layers through controlled lateral etching, the process mediates between the varying fin stack shapes and the requirement for uniform gate width, allowing the gate to be formed with consistent dimensions despite underlying structural variations.
3Manufacturing precision
If uniform gate width is achieved through varying sacrificial layer characteristics, then device performance is improved, but the fabrication process becomes more complex
Solution Approach 1:
The patent achieves gate width uniformity by changing parameters of the sacrificial semiconductor layers, specifically varying germanium concentration or layer thickness across different regions. These parameter variations enable selective etching behavior that produces uniform gate width. While this adds some complexity to the fabrication process, it avoids the need for highly complex real-time control systems or multiple iterative adjustment steps, representing a balanced approach to manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method ensures a uniform gate width, improving device performance by stabilizing threshold voltage and enhancing overall functionality.
Implementation Method 1
By varying the characteristics of sacrificial semiconductor layers, such as germanium concentration or thickness, to control the etch rate during the patterning process
Data Source
AI summary
According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.