Nanostructure Gate Formation for Precise Threshold Voltage Tuning
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, challenges arise in integrating electronic components efficiently while maintaining performance, particularly in forming gate structures for nanostructures, where issues such as work function tuning layers degrading device performance and inaccurate threshold voltage control are prevalent.
Innovation Solution
The method involves forming work function tuning layers for n-type devices before p-type devices, using sacrificial layers to prevent contamination, and incorporating protection layers to inhibit diffusion, thereby allowing for more precise threshold voltage tuning and improved device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If work function tuning layers are formed for both n-type and p-type devices using the same process, then manufacturing simplicity is maintained, but threshold voltage control accuracy deteriorates due to cross-contamination and diffusion
Solution Approach 1:
The patent divides the gate structure formation process into separate sequences for n-type devices and p-type devices. Work function tuning layers are formed for n-type devices first, then sacrificial layers are removed and work function tuning layers are formed for p-type devices. This segmentation prevents cross-contamination and allows independent optimization of threshold voltage control for each device type, resolving the contradiction between manufacturing precision and process complexity.
Solution Approach 2:
The patent performs preliminary actions by forming work function tuning layers for n-type devices before forming those for p-type devices. Sacrificial layers are strategically placed and removed in advance to prepare the structure for subsequent work function tuning layer formation. This preliminary action ensures that each device type receives appropriate treatment without interference, improving threshold voltage control accuracy while managing process complexity through structured sequencing.
2Productivity
If feature sizes are reduced to increase integration density, then component integration density is improved, but manufacturing precision deteriorates due to difficulties in patterning and material deposition at smaller scales
Solution Approach 1:
The patent introduces sacrificial layers as intermediary structures that facilitate precise formation of gate structures at reduced feature sizes. These sacrificial layers serve as temporary placeholders and masks during the manufacturing process, enabling accurate positioning and deposition of work function tuning layers even at small dimensions. After the work function tuning layers are formed, the sacrificial layers are removed. This intermediary approach maintains manufacturing precision while allowing continued scaling for higher integration density.
3Reliability
If work function tuning layers are formed without protection layers, then process simplicity is maintained, but device performance deteriorates due to diffusion and contamination
Solution Approach 1:
The patent introduces protection layers as intermediary structures that prevent diffusion and contamination of work function tuning layers during subsequent processing steps. These protection layers are formed over the work function tuning layers after they are deposited, creating a barrier that maintains material integrity and prevents harmful interactions with other process materials. The protection layers are removed after serving their protective function. This intermediary protection mechanism ensures device performance reliability while managing process complexity through targeted protection only where needed.
Data Source
AI summary
An embodiment includes a device having a first set of nanostructures on a substrate, the first set of nanostructures including a first channel region, a second set of nanostructures on the substrate, the second set of nanostructures including a second channel region, a gate dielectric layer wrapping around each of the first and second sets of nanostructures, a first work function tuning layer on the gate dielectric layer of the first set of nanostructures, the first work function tuning layer wrapping around each of the first set of nanostructures, a glue layer on the first work function tuning layer, the glue layer wrapping around each of the first set of nanostructures, a second work function tuning layer on the glue layer of the first set of nanostructures and on the gate dielectric layer of the second set of nanostructures, and a fill layer on the second work function tuning layer.