Nanostructure Transistor High-k Profile to Reduce Parasitic Capacitance
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Solution Overview
Problem
Existing semiconductor device fabrication processes face challenges in reducing parasitic capacitance and RC delay in non-planar transistor devices, particularly in nanostructure transistors, which affect device performance and integration density.
Innovation Solution
A method involving selective etching to form a high-k dielectric structure with a wider and shallower profile, including a combination of etching steps to create tilted and plateau portions in the nitride-based dielectric and cladding layers, which reduces parasitic capacitance between gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication processes are used, then manufacturing simplicity is maintained, but parasitic capacitance and RC delay increase, reducing device performance
Solution Approach 1:
The fabrication process is divided into multiple selective etching steps, each targeting specific layers (nitride-based dielectric layer, cladding layer, oxide-based layer) with different etch selectivities. This segmentation allows precise control over the high-k dielectric structure profile, creating tilted and plateau portions that reduce parasitic capacitance while maintaining manageable process complexity through systematic breakdown of the fabrication sequence
Solution Approach 2:
The patent applies local quality by creating non-uniform etching profiles in different regions of the structure. The selective etching process produces tilted portions at the edges and plateau portions at the center of the high-k dielectric structure, with each region having different geometries optimized for reducing parasitic capacitance. This local differentiation of structural properties enables targeted reduction of harmful electrical effects while preserving overall device functionality
2Productivity
If feature size is reduced to increase integration density, then more components can be integrated, but parasitic capacitance effects become more significant, degrading device performance
Solution Approach 1:
The patent addresses parasitic capacitance in the lateral dimension by creating a wider high-k dielectric structure through selective etching. By modifying the horizontal profile to include tilted and plateau portions, the invention effectively increases the spacing between adjacent gate structures in the lateral direction, thereby reducing parasitic capacitance coupling. This dimensional approach allows integration density to increase while parasitic effects are mitigated through lateral profile control rather than vertical scaling alone
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Significantly reduces parasitic capacitance by up to 1.6%, thereby minimizing parasitic delay and enhancing device performance and integration density in nanostructure transistors.
Implementation Method 1
a portion of the nitride-based dielectric layer and a portion of the cladding layer are selectively etched
Implementation Method 2
filling the recess with high-k dielectric material
Data Source
AI summary
A semiconductor device includes a first channel structure extending along a first lateral direction and a second channel structure extending along the first lateral direction. The second channel structure is spaced apart from the first channel structure. The semiconductor device further includes a high-k dielectric structure extending along the first lateral direction and disposed between the first and second channel structures. The high-k dielectric structure has a bottom surface that comprises a bottommost portion and at least a first plateau portion elevated from the bottommost portion.