Nanostructure Protection Layers for Reliable Gate-All-Around Etching
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Solution Overview
Problem
The challenge of forming reliable semiconductor devices at smaller sizes is exacerbated by the increasing complexity of fabrication processes as feature sizes continue to decrease, making it difficult to maintain device integrity and performance.
Innovation Solution
A method involving the use of multiple protection layers and precise etching processes to protect and pattern nanostructures, such as nanowires and nanosheets, within semiconductor devices, ensuring structural integrity and enhancing the reliability of the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency is improved and costs are lowered, but fabrication process complexity increases and device reliability deteriorates
Solution Approach 1:
The patent divides the protection structure into multiple segments: a first protection layer (silicon nitride) and a second protection layer (silicon oxide) with different thicknesses and positions. The first protection layer is thicker at the bottom to protect against etching from below, while the second protection layer is thicker at the top to protect against etching from above, creating a segmented protection strategy that addresses different vulnerability zones
Solution Approach 2:
The patent applies different protection layer thicknesses at different locations: the first protection layer has greater thickness at the bottom portion compared to the top portion, and the second protection layer has greater thickness at the top portion compared to the bottom portion. This local variation in protection quality optimizes etching resistance where most needed while reducing material usage elsewhere
2Productivity
If feature sizes continue to decrease to increase functional density, then scaling benefits are achieved, but fabrication process difficulty increases
Solution Approach 1:
The patent forms protection layers on the nanostructure stack before performing etching operations. The first protection layer is deposited and partially removed, then the second protection layer is deposited and patterned, creating a prepared protective structure that enables subsequent etching processes to proceed with greater precision and less risk of damage to the underlying nanostructures
Solution Approach 2:
The protection layers serve as intermediary structures between the etching process and the nanostructure stack. These intermediate layers absorb the harsh effects of etching chemicals and physical processes, mediating the interaction between the etching tools and the delicate nanostructures, thereby reducing direct damage and improving manufacturing ease
Data Source
AI summary
A method for forming a semiconductor device structure is provided. The method includes providing a substrate and a nanostructure stack. The method includes forming an isolation layer over the base and surrounding the fin. The method includes forming a first protection layer over the nanostructure stack and the isolation layer. The method includes forming a second protection layer over the first protection layer. The method includes forming a mask layer over the second protection layer. The top portion of the second protection layer protrudes from the mask layer. The method includes thinning the top portion of the second protection layer. The method includes removing the mask layer. The method includes removing the first protection layer and the second protection layer over the nanostructure stack. The method includes forming a gate stack wrapped around the nanostructure stack.