Nanostructure Semiconductor Light Emitting Device Stress Control
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Solution Overview
Problem
Nanostructure semiconductor light emitting devices face challenges in achieving high indium incorporation and reduced structural stress, leading to difficulties in emitting long wavelength light due to low indium incorporation rates and stacking fault defects in active layers.
Innovation Solution
Incorporating a stress control layer with a superlattice structure containing indium between the nanocore and active layer, where the indium content and thickness of each layer are optimized to alleviate lattice constant differences, enhancing indium incorporation and reducing crystal defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a non-polar plane (m-plane) is used for growing the active layer, then the device efficiency is improved by preventing polarization degradation, but the indium incorporation ratio decreases making it difficult to achieve long wavelength emission
Solution Approach 1:
The patent divides the active layer into multiple quantum well layers with different indium compositions arranged in a specific sequence. This segmentation allows each layer to contribute differently to the overall emission characteristics, enabling high indium incorporation in specific layers while maintaining device efficiency through the non-polar m-plane structure.
Solution Approach 2:
The patent applies local quality by creating quantum well layers with spatially varying indium compositions (different y values in InyGa1-yN). Specific regions have higher indium content for long wavelength emission while other regions have lower indium content to maintain structural stability and prevent defects, all grown on the m-plane to preserve device efficiency.
2Ease of manufacture
If the indium content in the active layer is increased to achieve long wavelength emission, then the emission wavelength increases, but stacking fault defects occur due to lattice constant mismatch with the nanocore
Solution Approach 1:
The patent changes the indium composition parameter (y value) progressively across different quantum well layers. By carefully controlling the indium content in each layer and arranging them in a specific sequence, the patent achieves long wavelength emission while managing lattice constant differences to minimize stacking fault defects.
Solution Approach 2:
The patent introduces a stress control layer between the nanocore and the active layer before growing the high indium-content quantum wells. This preliminary action compensates for lattice mismatch stress in advance, preventing stacking fault defects that would otherwise occur when growing high indium content layers on the nanocore.
3Reliability
If a stress control layer with optimized indium content and thickness is introduced, then the indium incorporation in the active layer is enhanced and crystal defects are reduced, but the device structure becomes more complex
Solution Approach 1:
The patent introduces a stress control layer as an intermediary between the nanocore and the active layer. This intermediate layer has specific indium content and thickness that are optimized to compensate for lattice mismatch stress, thereby enhancing indium incorporation in the subsequent active layer and reducing crystal defects while adding only one additional functional layer.
Data Source
AI summary
There is provided a nanostructure semiconductor light emitting device including a base layer formed of a first conductivity-type nitride semiconductor and a plurality of light emitting nanostructures disposed to be spaced apart from one another on the base layer. Each of the plurality of light emitting nanostructures includes a nanocore formed of the first conductivity-type nitride semiconductor, a stress control layer disposed on a surface of the nanocore and including a nitride semiconductor containing indium, an active layer disposed on the stress control layer and including a nitride semiconductor containing indium, and a second conductivity-type nitride semiconductor layer disposed on the active layer.