Nanostructure Source/Drain Contacts for Lower Silicide Resistance
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Solution Overview
Problem
As semiconductor devices continue to integrate more components into a given area with reduced minimum feature sizes, challenges arise in reducing electrical resistance between epitaxial source/drain regions and silicide layers, affecting device performance.
Innovation Solution
The implementation of larger contact areas between epitaxial source/drain regions and silicide layers is achieved by forming epitaxial source/drain regions on fins and nanostructures, which are then connected to silicide layers, thereby reducing electrical resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but electrical resistance between epitaxial source/drain regions and silicide layers increases
Solution Approach 1:
The patent transitions from planar contacts to three-dimensional contacts by forming epitaxial source/drain regions that extend vertically along the sidewalls of gate structures. This vertical extension into the third dimension increases the contact area between the epitaxial regions and silicide layers without increasing the lateral footprint, thereby maintaining integration density while reducing electrical resistance through enhanced contact area.
Solution Approach 2:
The patent applies different material compositions and structures to specific local regions. The epitaxial source/drain regions are formed with specific doping concentrations and material compositions (e.g., SiGe) in localized areas to optimize electrical properties. The silicide layers are selectively formed only in contact regions rather than uniformly across the structure, creating locally optimized low-resistance pathways where needed most.
2Reliability
If contact area between epitaxial source/drain regions and silicide layers is increased to reduce electrical resistance, then device performance improves, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming the epitaxial source/drain regions with extended sidewall structures before final silicide deposition. The epitaxial growth process is configured in advance to create the desired three-dimensional contact geometry, and selective masking patterns are prepared beforehand to ensure silicide forms only in the intended contact regions. This preliminary structuring simplifies subsequent processing steps and reduces overall manufacturing complexity.
Solution Approach 2:
The patent introduces epitaxial source/drain regions as intermediary structures that mediate between the gate structures and the silicide contact layers. These intermediary regions provide a controlled interface that facilitates reliable electrical contact while maintaining structural integrity. The epitaxial regions act as a buffer zone that simplifies the integration of different material systems and reduces manufacturing challenges associated with direct metal-to-semiconductor contacts.
Data Source
AI summary
A semiconductor device and the method of forming the same are provided. The semiconductor device may comprise a first plurality of nanostructures, a second plurality of nanostructures over a substrate, a first gate stack extending between the nanostructures of the first plurality of nanostructures, a second gate stack extending between the nanostructures of the second plurality of nanostructures, a first source/drain region in contact with a first nanostructure of the first plurality of nanostructures, a second source/drain region in contact with a first nanostructure of the second plurality of nanostructures, wherein the second source/drain region may be separated from the first source/drain region, a silicide layer between the first source/drain region and the second source/drain region, and an isolation layer between the silicide layer and the substrate.