Nanostructure Transistor Sacrificial Spacers for Clean Gate Metal Deposition
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Solution Overview
Problem
As semiconductor devices shrink in size, they face issues such as short channel effects, hot carrier degradation, barrier lowering, and increased source/drain electron tunneling, leading to off-currents and reduced power efficiency in silicon/silicon germanium nanostructure transistors like nanowires and gate-all-around devices.
Innovation Solution
The integration of sacrificial spacers and anisotropic wet etching techniques in the formation of nanostructure transistors, along with sequential work function metal layer deposition, enhances control over gate structures, reduces material residue, and minimizes seam formation, thereby improving threshold voltage stability and power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If gate length is reduced for smaller technology nodes, then transistor size decreases, but source/drain electron tunneling increases leading to higher off current
Solution Approach 1:
The patent applies preliminary action by forming sacrificial spacers before gate deposition to define precise source/drain regions. This pre-structuring prevents electron tunneling by establishing proper spatial separation between source and drain regions before the gate is formed, addressing the tunneling issue that arises from reduced gate length.
Solution Approach 2:
The sacrificial spacers act as intermediary structures that mediate between the source and drain regions. These spacers are temporarily introduced to control the spacing and prevent direct electron tunneling, then removed after serving their protective function during gate formation.
2Ease of manufacture
If conventional etching methods are used, then manufacturing process is simpler, but material residue and seam formation increase reducing threshold voltage stability
Solution Approach 1:
The patent replaces conventional mechanical or plasma etching methods with wet chemical etching. This substitution achieves superior material residue removal and seam prevention through chemical dissolution, providing better manufacturing precision while maintaining process simplicity. The wet etchant selectively removes sacrificial spacer material without damaging surrounding structures.
Solution Approach 2:
The patent changes the etching parameter from dry/plasma to wet chemical etching. This parameter change fundamentally alters the removal mechanism, enabling complete dissolution of sacrificial spacer material and elimination of seams that would otherwise form during gate deposition, thereby stabilizing threshold voltage.
3Device complexity
If work function metal layer is deposited without sacrificial spacers, then device complexity is reduced, but material deposition between vertically adjacent nanostructure channels increases
Solution Approach 1:
Sacrificial spacers serve as intermediary protective structures during metal deposition. They temporarily occupy the spaces between vertically adjacent nanostructure channels, preventing work function metal from depositing in these regions. After deposition, the spacers are removed, leaving clean interfaces and precise material placement.
Solution Approach 2:
The patent extracts or removes the sacrificial spacers after they have served their protective function during metal deposition. This extraction eliminates the temporary structures and prevents any potential interference with device operation, while having already achieved the goal of preventing unwanted metal deposition.
4Length of moving object
If nanoscale transistor dimensions are used, then device size decreases, but short channel effects such as hot carrier degradation increase
Solution Approach 1:
The patent applies preliminary action by forming sacrificial spacers and defining source/drain regions before gate formation. This pre-structuring ensures proper electrical isolation and spatial definition at nanoscale dimensions, preventing short channel effects by establishing well-defined potential barriers before the gate is formed.
Solution Approach 2:
The patent segments the transistor structure into clearly defined regions using sacrificial spacers. This segmentation creates distinct source, drain, and channel regions with proper boundaries, preventing the merging of regions that occurs in short channel devices and thereby reducing hot carrier degradation and other short channel effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces short channel effects, increases drive current, and enhances the performance of complementary metal oxide semiconductor integrated circuits by stabilizing threshold voltages and minimizing current leakage in both PMOS and NMOS nanostructure transistors.
Implementation Method 1
etching, using a wet etchant, the sacrificial spacer layer to remove first portions of the sacrificial spacer layer from sides of the plurality of nanostructure channels
Implementation Method 2
Hydrogen (H+) ions in the wet etchant inhibit etching of the sacrificial spacers between the vertically adjacent nanostructure channels
Implementation Method 3
forming a work function metal layer on the plurality of nanostructure channels
Data Source
AI summary
Sacrificial spacers are formed between vertically adjacent nanostructure channels of a first nanostructure transistor to prevent or reduce the likelihood of material from a work function metal layer of a second nanostructure transistor being deposited between the vertically adjacent nanostructure channels. A sacrificial spacer layer is formed around the nanostructure channels of the first nanostructure channel and then etched such that the sacrificial spacer layer remains only between vertically adjacent nanostructure channels of the first nanostructure transistor as the sacrificial spacers. An anisotropic wet etch technique is used to etch the sacrificial spacer layer such that seams in the sacrificial spacer layer are not widened by the etching. This increases the likelihood that the material of the work function metal layer of the second nanostructure transistor will be fully removed from the first nanostructure transistor prior to formation of a work function metal layer of the second nanostructure transistor.