Nanostructure Transistor Gate Layout With Split Gate Lengths
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integration of gate-all-around (GAA) devices in semiconductor manufacturing is challenging due to complexity in fabricating the GAA features around nanowires, necessitating improved methods for forming semiconductor structures that enhance gate control and reduce short-channel effects.
Innovation Solution
A semiconductor structure is developed with nanostructure transistors featuring a top gate electrode layer with a shorter gate length and an inner gate electrode layer with a longer gate length, utilizing double-patterning or multi-patterning processes to create smaller pitches, and incorporating epitaxial stacks of alternating semiconductor layers to form nanowires or nanosheets as channels, along with spacer layers to improve device density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional single-gate structures are used, then manufacturing is simpler, but gate control is insufficient and short-channel effects increase
Solution Approach 1:
The patent implements a gate-all-around structure where an inner gate electrode is nested within a outer gate electrode, both surrounding the channel region. This nested configuration provides enhanced gate control from multiple directions while managing the complexity through systematic layering of gate structures.
Solution Approach 2:
The patent transitions from planar single-gate control to three-dimensional gate-all-around control by extending gate electrodes around the channel region in vertical and lateral dimensions. This dimensional expansion improves gate control effectiveness by contacting the channel from all sides.
2Quantity of substance
If multi-patterning processes are used to create smaller pitches, then device density improves, but manufacturing complexity increases
Solution Approach 1:
The patent divides the gate formation into multiple patterning steps, creating different gate length regions through sequential patterning operations. This segmentation enables precise control of gate dimensions and facilitates higher device density while managing manufacturing complexity through standardized process modules.
Solution Approach 2:
The patent performs preliminary patterning actions to define gate regions before final gate electrode formation. By pre-establishing pattern guidelines and performing initial structuring steps, the process enables subsequent gate fabrication with improved precision and reduced overall manufacturing complexity.
3Quantity of substance
If gate length is reduced to increase device density, then more devices fit in smaller area, but gate leakage and off-state current increase
Solution Approach 1:
The patent implements varying gate lengths in different regions of the device structure. The inner gate and outer gate can have different length dimensions, allowing optimization of gate control in specific local areas while maintaining overall high device density. This local differentiation addresses leakage issues in critical regions without sacrificing density elsewhere.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances gate control, reduces gate leakage and off-state current, and improves the density and performance of semiconductor devices by leveraging the unique structure of nanostructure transistors.
Implementation Method 1
incorporating epitaxial stacks of alternating semiconductor layers to form nanowires or nanosheets as channels
Data Source
AI summary
A semiconductor structure is provided. The semiconductor structure includes a first set of nanostructures that are stacked vertically and spaced apart from one another and formed in a first well, a source/drain feature adjoining the first set of nanostructures, a first top gate electrode layer above a topmost nanostructure in the first set of nanostructures, and an inner gate electrode layer sandwiched between the nanostructures. A first dimension of the inner gate electrode layer in a first direction is greater than a second dimension of the first top gate electrode layer in the first direction.