Nanostructure Transistor Superlattice for Dopant Blocking and Mobility
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Solution Overview
Problem
Current semiconductor devices face limitations in enhancing charge carrier mobility and performance due to issues like alloy scattering, sub-stoichiometric insulating properties, and unwanted scattering effects at interfaces.
Innovation Solution
The implementation of a semiconductor superlattice structure with alternating layers of silicon and non-semiconductor materials like oxygen, which reduces charged impurity concentration, improves interface quality, and acts as a dopant and diffusion barrier, enhancing charge carrier mobility and providing piezoelectric, pyroelectric, and ferroelectric properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If strained material layers of silicon and silicon-germanium are used to enhance carrier mobility, then device speed and performance are improved, but alloy scattering and interface defects increase causing performance degradation
Solution Approach 1:
The patent segments the silicon layer into multiple thin layers (first silicon layer, second silicon layer) separated by a dopant blocking structure. This segmentation allows the introduction of strained silicon-germanium layers without creating continuous alloy scattering paths, as the dopant blocking structure interrupts the alloy region while maintaining strain benefits in each silicon segment.
Solution Approach 2:
The patent introduces a dopant blocking structure as an intermediary between source/drain regions and the silicon channel layers. This intermediary structure prevents dopant diffusion into the channel while also serving as a barrier that reduces alloy scattering effects, allowing strained silicon-germanium layers to enhance carrier mobility without the harmful effects of continuous alloying.
2Reliability
If dopant blocking structures are formed to prevent dopant diffusion, then junction integrity is improved, but misalignment and non-flush interfaces cause unwanted scattering effects
Solution Approach 1:
The patent applies local quality by forming the dopant blocking structure with different regions having different functions: a first region that provides dopant blocking and a second region that is substantially flush with the insulating region to provide a smooth interface. This local differentiation allows the structure to simultaneously achieve dopant blocking and minimize interface scattering.
Solution Approach 2:
The patent performs preliminary action by forming the dopant blocking structure before final source/drain region formation, ensuring that the structure is already in place to prevent dopant diffusion. The structure is formed with a substantially flush interface from the beginning, preventing interface misalignment issues that would cause scattering effects during subsequent processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach leads to improved charge carrier mobility, reduced scattering effects, and enhanced performance in semiconductor devices, including higher mobility and direct energy bandgap characteristics suitable for opto-electronic applications.
Implementation Method 1
forming respective dopant blocking superlattices adjacent lateral ends of the nanostructures
Implementation Method 2
acts as a dopant and diffusion barrier, enhancing charge carrier mobility
Implementation Method 3
providing piezoelectric, pyroelectric, and ferroelectric properties
Implementation Method 4
providing piezoelectric, pyroelectric, and ferroelectric properties
Implementation Method 5
reduces charged impurity concentration, improves interface quality, and acts as a dopant and diffusion barrier, enhancing charge carrier mobility
Data Source
AI summary
A method for making a semiconductor device may include forming spaced apart gate stacks on a substrate defining respective trenches therebetween. Each gate stack may include alternating layers of first and second semiconductor materials, with the layers of the second semiconductor material defining nanostructures. The method may further include forming respective source/drain regions within the trenches, forming respective insulating regions adjacent lateral ends of the layers of the first semiconductor material, and forming respective dopant blocking superlattices adjacent lateral ends of the nanostructures and flush with adjacent surfaces of the insulating regions. Each dopant blocking superlattice may include stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.