Nanostructure Transistor Gate Stack Blocking for S/D Etch Protection
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Solution Overview
Problem
The scaling down of semiconductor integrated circuits poses a challenge as the source/drain (S/D) structure may suffer damage due to etchant leakage during the gate replacement process, despite the formation of inner spacers intended to protect it.
Innovation Solution
A blocking structure, typically a highly doped semiconductor material, is formed to seal the interface between the sacrificial gate dielectric and gate spacer, preventing etchant chemicals from reaching the S/D features and minimizing damage during the gate replacement process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If inner spacer is formed between metal gate and source/drain structure to protect S/D structure during gate replacement process, then S/D structure protection is improved, but etchant leakage still causes damage to S/D structure
Solution Approach 1:
A blocking structure comprising a first blocking layer and a second blocking layer is introduced as an intermediary element between the inner spacer and the source/drain structure. The first blocking layer is in contact with the inner spacer, while the second blocking layer is in contact with the source/drain structure, creating a dual-layer barrier that prevents etchant leakage from reaching and damaging the source/drain structure during gate replacement processes.
Solution Approach 2:
The blocking structure is formed in advance before the gate replacement process occurs, specifically before etchant chemicals are applied. This preliminary protective measure ensures that when etchant leakage occurs during subsequent processing steps, the blocking structure is already in place to absorb and contain the harmful effects, preventing direct contact between the etchant and the source/drain structure.
2Adaptability or versatility
If gate replacement process is performed to improve device performance, then device functionality is enhanced, but S/D structure damage occurs due to etchant leakage
Solution Approach 1:
The blocking structure serves as a protective intermediary that enables the gate replacement process to proceed while preventing harmful etchant leakage from reaching the source/drain structure. This intermediary layer allows manufacturers to perform necessary gate modifications for device performance improvement without compromising the structural integrity of the source/drain regions.
Solution Approach 2:
The blocking structure is prepared in advance through a multi-layer formation process involving selective epitaxial growth and doping, creating a robust protective barrier before the gate replacement process begins. This beforehand cushioning ensures that when etchant chemicals are introduced during gate replacement, the source/drain structure is already protected, allowing the process to complete successfully.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The blocking structure effectively prevents damage to the S/D features by blocking etchant leakage, preserving their integrity and reducing resistivity, thus enhancing the reliability and performance of nanostructure channel FETs.
Implementation Method 1
A blocking structure, typically a highly doped semiconductor material, is formed to seal the interface between the sacrificial gate dielectric and gate spacer, preventing etchant chemicals from reaching the S/D features
Implementation Method 2
A blocking structure, typically a highly doped semiconductor material, is formed to seal the interface
Data Source
AI summary
Various embodiments of the present disclosure provide a semiconductor device structure. In one embodiment, the semiconductor device structure includes a first source/drain feature and a second source/drain feature, a plurality of semiconductor layers vertically stacked and disposed between the first and second source/drain features, a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers, and an interfacial layer (IL) disposed between the gate electrode layer and one of the plurality of the semiconductor layers, wherein a topmost semiconductor layer of the plurality of the semiconductor layers has a first length, and the IL has a second length greater than the first length.