Nanostructure Transistor Hard Mask Layout for Lower Gate Capacitance
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Solution Overview
Problem
The increasing complexity and scaling down of integrated circuits have led to challenges in reducing gate-to-source/drain capacitance in nanostructure transistors, affecting their performance and efficiency.
Innovation Solution
The implementation of a hard mask structure above the stacked channels of a transistor, combined with the removal of the high-K gate dielectric layer from sidewalls and the implantation of dopant atoms into dielectric structures to reduce dielectric constant, results in reduced gate capacitance and improved electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-K gate dielectric layer is used to improve gate control, then gate control is improved, but gate-to-source/drain capacitance increases
Solution Approach 1:
The patent removes the high-K gate dielectric layer from the sidewalls of the gate electrode, extracting only the problematic portion that causes excessive capacitance while preserving the gate control function. This selective removal reduces the capacitive coupling between the gate and source/drain regions without compromising the overall gate control effectiveness.
Solution Approach 2:
The patent applies different dielectric properties to different regions: the high-K gate dielectric is retained in the channel region for effective gate control, while being removed from the sidewall regions where it causes harmful capacitance. This local differentiation optimizes both gate control and capacitance reduction.
2Productivity
If geometry size is decreased to increase functional density, then production efficiency increases, but manufacturing complexity increases
Solution Approach 1:
The patent forms the gate electrode structure with controlled dimensions before depositing the high-K gate dielectric layer. This preliminary structuring establishes precise geometric boundaries that guide subsequent dielectric deposition and removal steps, enabling better control over the final device dimensions and reducing manufacturing variability.
Solution Approach 2:
The gate structure is divided into distinct regions: the gate electrode, the channel region with high-K dielectric, and the sidewall regions where dielectric is removed. This segmentation allows independent optimization of each region's properties and simplifies the manufacturing process by breaking down complex steps into manageable segments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables transistors to operate at higher frequencies with superior electrical characteristics, enhancing wafer yields and overall integrated circuit function.
Implementation Method 1
the implantation of dopant atoms into dielectric structures to reduce dielectric constant
Data Source
AI summary
An integrated circuit includes a plurality of stacked channels, a hard mask structure above the channels, and a gate metal above the hard mask structure and wrapped around the channels. The integrated circuit includes a high-K gate dielectric layer wrapped around the channels, wherein a top of the hard mask structure is higher than a top of the high-K gate dielectric layer.