Nanostructure Transistor Sizing for Leakage and DIBL Control
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Solution Overview
Problem
As semiconductor device manufacturing advances, finFETs face challenges such as increased short channel effects and electron tunneling due to reduced technology processing nodes, leading to performance issues like current leakage and drain-induced barrier lowering, which are exacerbated by the similar properties of PMOS and NMOS nanostructure transistors in semiconductor devices, affecting device density and manufacturing costs.
Innovation Solution
The implementation of nanostructure transistors with varying channel widths and source/drain region dimensions for different device types, such as SRAM and RO devices, to reduce current leakage and drain-induced barrier lowering, while optimizing device density and manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If technology processing nodes are reduced to increase device density, then device density is improved, but short channel effects and electron tunneling increase causing current leakage
Solution Approach 1:
The patent applies local quality by giving different channel widths to PMOS and NMOS nanostructure transistors within the same device. Specifically, PMOS transistors are configured with a first channel width while NMOS transistors are configured with a second channel width that is different from the first. This localized differentiation allows each transistor type to be optimized for its specific electrical characteristics, reducing short channel effects and electron tunneling-induced current leakage while maintaining high device density through varied dimensional optimization.
2Quantity of substance
If gate length is reduced to increase device density, then device density is improved, but source/drain electron tunneling increases leading to higher off current
Solution Approach 1:
The patent applies parameter changes by varying the channel width parameter between PMOS and NMOS nanostructure transistors. By configuring PMOS transistors with a first channel width and NMOS transistors with a second channel width, the invention optimizes the electrical parameters of each transistor type to reduce source/drain electron tunneling effects. This parameter differentiation allows the device to maintain reduced gate lengths for high density while compensating for increased off current through tailored channel dimensions.
3Ease of manufacture
If uniform dimensions are used for all nanostructure transistors to simplify manufacturing, then manufacturing complexity is reduced, but device performance is compromised due to similar properties of PMOS and NMOS transistors
Solution Approach 1:
The patent implements local quality by configuring PMOS nanostructure transistors with a first channel width and NMOS nanostructure transistors with a second channel width. This localized dimensional differentiation optimizes the electrical performance of each transistor type, addressing the similar properties issue between PMOS and NMOS devices. The approach maintains manufacturing feasibility through a systematic dimensioning strategy while significantly improving device performance through tailored channel dimensions for each transistor type.
Data Source
AI summary
Some implementations described herein provide a semiconductor device and methods of formation. The semiconductor device may include one or more device types, such as a static random access memory device type, a ring oscillator device type, and/or an input/output device type. A device type may include an n-type metal oxide semiconductor nanostructure transistor and a p-type metal oxide semiconductor nanostructure transistor. In such a case, nanostructure channels of the n-type metal oxide semiconductor nanostructure transistor may have a width that is lesser relative to a width of nanostructure channels of the p-type metal oxide semiconductor nanostructure transistor. Additionally, or alternatively, other properties of the nanostructure transistors, such as a gate length or a width of a source/drain region, may vary based on the device type.