Nanostructure Transistor Layout to Prevent Source/Drain Merging
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Solution Overview
Problem
As semiconductor devices miniaturize, nanostructure transistors face challenges such as increased defect rates due to source/drain region merging, leading to electrical shorting and reduced yield, exacerbated by short channel effects and electron tunneling.
Innovation Solution
The source/drain regions in nanostructure transistors are staggered to increase the distance between them, reducing the likelihood of merging and enhancing yield, while maintaining device performance through vertical nanostructure channels and gate structures that wrap around the channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If source/drain regions are positioned closer together to enable miniaturization, then device density increases, but defect rates increase due to region merging and electrical shorting
Solution Approach 1:
The patent introduces a vertical dimension to separate source and drain regions by staggering them at different heights within the channel structure. This vertical offset prevents lateral merging of source/drain regions while maintaining horizontal proximity, thereby increasing device density without compromising yield.
Solution Approach 2:
The source and drain regions are nested within the channel structure at different vertical levels, with one region positioned above the other. This nesting arrangement allows compact packaging while maintaining electrical isolation between regions, resolving the contradiction between miniaturization and defect prevention.
2Length of moving object
If gate length is reduced for smaller technology nodes, then device miniaturization is achieved, but off current increases due to source/drain electron tunneling
Solution Approach 1:
By staggering source and drain regions vertically, the patent increases the effective tunneling distance even when gate length is reduced. This vertical separation adds a dimensional factor to the tunneling barrier, suppressing off-current while allowing continued gate length scaling.
3Reliability
If source/drain regions are staggered vertically to prevent merging, then yield is improved, but device complexity increases
Solution Approach 1:
The patent forms the staggered source/drain regions during the initial epitaxial growth stage, establishing the vertical offset before subsequent processing steps. This preliminary formation of the staggered structure simplifies later fabrication steps compared to attempting to create the offset through multiple alignment steps.
Data Source
AI summary
Nanostructure transistors are formed in a manner that may reduce the likelihood of source/drain region merging in the nanostructure transistors. In a top-down view of a nanostructure transistor described herein, source/drain regions on opposing sides of a nanostructure channel of the nanostructure transistor are staggered such that that distance between the source/drain regions is increased. The reduces the likelihood of the source/drain regions merging, which reduces the likelihood of failures and/or other defects forming in the nanostructure transistor. Accordingly, staggering the source/drain regions, as described herein, may facilitate the miniaturization of semiconductor devices that include nanostructure transistors while maintaining and/or increasing the semiconductor device yield of the semiconductor devices.