Nanostructure Transistor Source/Drain Seed Layer for Uniform Epitaxy

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Solution Overview

Problem

As semiconductor devices continue to shrink in size, defects and non-uniformity in source/drain regions become significant challenges, affecting device performance and yield.

Innovation Solution

Forming source/drain regions on a continuous seed layer and using inner spacers to improve uniformity and reduce defects, with a hard mask protecting the nanostructures during the process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but defects and non-uniformity in source/drain regions increase

Engineering Contradiction:
Improveintegration densityVSAvoiduniformity of source/drain regions
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

A seed layer is formed in the source/drain region before the main source/drain material is deposited. This preliminary layer provides a uniform foundation that guides subsequent material deposition, ensuring consistent thickness and composition even as feature sizes shrink. The seed layer is formed through preliminary epitaxial growth or deposition processes that establish atomic-level uniformity before the main growth phase.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The seed layer acts as an intermediary between the substrate and the main source/drain material. It mediates the interface properties, providing a transition zone that ensures uniform material deposition and reduces defects. The seed layer intermediate structure allows for better control of material properties and reduces the direct impact of substrate variations on the final source/drain region quality.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but device performance deteriorates due to defects

Engineering Contradiction:
Improveintegration densityVSAvoiddevice performance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The seed layer is formed in advance with controlled composition and structure to prevent defects before the main source/drain material is deposited. This preliminary preparation ensures that the epitaxial growth starts from a uniform, defect-free interface, maintaining device performance despite smaller feature sizes. The seed layer composition can be optimized beforehand to match the desired final material properties.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The seed layer allows for parameter optimization in the source/drain region formation process. By controlling the seed layer thickness, composition, and growth conditions, the final source/drain material can be grown with improved crystalline quality and reduced defects. Parameters such as temperature, pressure, and material flux can be optimized during seed layer formation to ensure high-quality device performance at scaled dimensions.

Inventive Principle:
Principle #35Parameter changes

3Ease of manufacture

If conventional source/drain formation is used without seed layer, then process is simpler, but defects and non-uniformity increase

Engineering Contradiction:
Improveprocess simplicityVSAvoiduniformity of source/drain regions
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The seed layer formation is integrated into the existing manufacturing process flow as a preliminary step before source/drain material deposition. This additional layer is formed using standard epitaxial or deposition equipment already present in the fabrication line, minimizing the need for new process equipment while significantly improving uniformity. The seed layer formation can be combined with other process steps to minimize additional process complexity.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250318168A1Nanostructure transistors and methods of forming the same
Publication Date: 2025.10.09 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250318168A1 patent drawing
  • US20250318168A1 patent drawing
  • US20250318168A1 patent drawing

AI summary

A method includes forming a stack of nanostructures over a substrate; forming a recess in the substrate adjacent the stack of nanostructures, wherein the recess exposes sidewalls of the stack of nanostructures; depositing a continuous semiconductor seed layer in the recess and extending along the sidewalls of the stack of nanostructures; epitaxially growing a source/drain region on the semiconductor seed layer; after epitaxially growing the source/drain region, forming inner spacers between adjacent nanostructures of the stack of nanostructures; and forming a gate structure between adjacent nanostructures of the stack of nanostructures.