Nanostructure Transistor Source/Drain Growth on a Continuous Seed Layer

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Solution Overview

Problem

As semiconductor devices continue to shrink in size, defects and non-uniformity in source/drain regions become significant challenges, affecting device performance and yield.

Innovation Solution

The formation of source/drain regions on a continuous seed layer, with the use of inner spacers and a hard mask to protect nanostructures, enhances the uniformity and reduces defects, thereby improving device performance and density.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If minimum feature size is reduced to improve integration density, then more components can be integrated into a given area, but defects and non-uniformity in source/drain regions increase

Engineering Contradiction:
Improveintegration densityVSAvoiduniformity of source/drain regions
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

A seed layer is formed prior to the source/drain regions to provide a foundation that promotes uniformity. The seed layer is deposited and prepared in advance before the actual source/drain formation process, allowing it to establish a consistent base that guides subsequent material deposition and reduces defects in the final source/drain structures.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The seed layer acts as an intermediary between the substrate and the source/drain regions. This intermediate layer mediates the interface properties, ensuring better adhesion and more uniform characteristics in the source/drain regions that form on top of it, thereby reducing defects while maintaining small feature sizes.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If minimum feature size is reduced to improve integration density, then more components can be integrated into a given area, but device performance deteriorates due to defects

Engineering Contradiction:
Improveintegration densityVSAvoiddevice performance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The seed layer is prepared in advance to establish a uniform foundation that prevents defects during source/drain formation. This preliminary preparation ensures that even at reduced feature sizes, the source/drain regions maintain the quality and uniformity needed for reliable device operation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The seed layer serves as a mediating structure that protects the device performance by providing a controlled interface. This intermediary layer ensures that the source/drain regions form with fewer defects, maintaining device reliability despite the reduced feature sizes required for high integration density.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If source/drain regions are formed without a seed layer to simplify the process, then manufacturing steps are reduced, but defects and non-uniformity increase

Engineering Contradiction:
Improvenumber of manufacturing stepsVSAvoiduniformity of source/drain regions
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The seed layer is deposited as a preliminary step before source/drain formation. This early preparation creates a uniform base that guides subsequent material deposition, ensuring consistent source/drain region characteristics without requiring complex control during the actual formation process.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The seed layer acts as an intermediary that simplifies the overall process by providing a self-organizing foundation. Rather than requiring complex in-situ control during source/drain formation, the seed layer pre-establishes the conditions needed for uniform growth, reducing the need for additional manufacturing steps.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20250351396A1Nanostructure transistors and methods of forming the same
Publication Date: 2025.11.13 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250351396A1 patent drawing
  • US20250351396A1 patent drawing
  • US20250351396A1 patent drawing

AI summary

A method includes forming a stack of nanostructures over a substrate; forming a recess in the substrate adjacent the stack of nanostructures, wherein the recess exposes sidewalls of the stack of nanostructures; depositing a continuous semiconductor seed layer in the recess and extending along the sidewalls of the stack of nanostructures; epitaxially growing a source/drain region on the semiconductor seed layer; after epitaxially growing the source/drain region, forming inner spacers between adjacent nanostructures of the stack of nanostructures; and forming a gate structure between adjacent nanostructures of the stack of nanostructures.