Multi-Material Nanostructure Transistor for Threshold Voltage Control
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Solution Overview
Problem
As semiconductor technology advances, the challenge of further improving nanostructure FETs for higher device density, performance, and lower costs remains, particularly in maintaining effective gate control and reducing short-channel effects.
Innovation Solution
The solution involves a semiconductor device structure with multiple semiconductor layers of different materials and compositions, which are used to create nanostructure channels surrounded by a gate electrode, allowing for multiple threshold voltages and improved device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor dimensions are scaled down to increase device density, then productivity and production efficiency improve, but gate control deteriorates and short-channel effects increase
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional nanostructure channels (nanowires, nanosheets, or vertical fins) that can be surrounded by the gate electrode on multiple sides. This dimensional change allows the gate to control the channel from top, bottom, and sidewalls simultaneously, maintaining effective gate control even as the channel length is scaled down to increase device density.
Solution Approach 2:
The gate electrode is positioned to surround the nanostructure channel in a nested configuration, with the gate wrapping around the channel from multiple directions. This nested arrangement enables the gate to envelop the channel completely, providing superior electrostatic control and reducing short-channel effects while allowing continued scaling for higher device density.
2Ease of manufacture
If conventional planar FET structures are used, then manufacturing is simpler, but gate control and performance are limited
Solution Approach 1:
The channel is segmented into multiple thin semiconductor layers (nanosheets or stacked nanowires) instead of using a single thick planar channel. This segmentation allows the gate to control each layer individually and provides better electrostatic control overall, while the layered structure can be fabricated using sequential deposition and etching processes that build upon conventional manufacturing techniques.
Solution Approach 2:
The patent employs composite semiconductor structures combining different materials with varying bandgaps and carrier mobilities in the multi-layer channel. This composite approach enables tailored electrical characteristics and improved gate control, while the modular layered architecture can be integrated into existing fabrication workflows through adapted deposition and processing steps.
3Ease of manufacture
If single-material semiconductor layers are used, then manufacturing is easier, but device performance and threshold voltage control are limited
Solution Approach 1:
Different semiconductor layers in the stacked channel structure are assigned different materials with distinct bandgap energies and carrier properties. This local differentiation enables independent threshold voltage control for each layer, allowing the device to achieve multiple threshold voltages and enhanced performance characteristics, while each layer can be processed using material-specific optimized techniques.
Solution Approach 2:
The patent varies material composition, layer thickness, and doping concentrations across different semiconductor layers to achieve desired electrical characteristics. By changing these parameters locally in each layer, the device can be tuned for specific applications with different threshold voltage requirements, maintaining manufacturing feasibility through controlled deposition and doping processes.
Data Source
AI summary
A transistor is provided. The transistor includes a first source/drain epitaxial feature, a second source/drain epitaxial feature, and two or more semiconductor layers disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The two or more semiconductor layers comprise different materials. The transistor further includes a gate electrode layer surrounding at least a portion of the two or more semiconductor layers, wherein the transistor has two or more threshold voltages.