Nanostructure Transistor Trench Contact Liners for Higher Mobility
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Solution Overview
Problem
Existing semiconductor devices face limitations in achieving enhanced charge carrier mobility and performance due to challenges in material interfaces and scattering effects.
Innovation Solution
The introduction of an enhanced semiconductor superlattice, referred to as MST technology, which incorporates alternating layers of semiconductor and non-semiconductor materials to reduce effective mass of charge carriers, improve interface quality, and act as a barrier to dopant diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor structures are used, then manufacturing simplicity is maintained, but charge carrier mobility is limited due to scattering effects and interface quality issues
Solution Approach 1:
The semiconductor structure is divided into multiple alternating layers of different materials (e.g., Si/SiGe/Si) forming a superlattice. Each layer has specific thickness and composition designed to reduce scattering effects and improve interface quality, thereby enhancing charge carrier mobility without requiring complete redesign of the manufacturing process
Solution Approach 2:
The patent employs composite material structures where alternating layers of semiconductor materials with different properties (e.g., silicon and silicon-germanium) are combined to create a superlattice. This composite structure exploits the beneficial properties of each material to reduce scattering and improve interface quality, achieving higher charge carrier mobility
2Reliability
If strained material layers are introduced to enhance mobility, then charge carrier mobility improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent systematically varies parameters such as layer thickness, composition ratio, and strain magnitude in the alternating layers to optimize charge carrier mobility. By controlling these parameters within specific ranges, the design achieves enhanced mobility while maintaining compatibility with existing manufacturing precision capabilities
3Reliability
If multiple alternating layers are formed to reduce scattering effects, then charge carrier mobility is enhanced, but device complexity increases
Solution Approach 1:
The semiconductor structure is divided into multiple alternating layers of different materials (e.g., Si/SiGe/Si) forming a superlattice. Each layer has specific thickness and composition designed to reduce scattering effects and improve interface quality, thereby enhancing charge carrier mobility without requiring complete redesign of the manufacturing process
Solution Approach 2:
The alternating layer structure serves multiple functions simultaneously: it creates strain to enhance mobility, provides interfaces for scattering reduction, and maintains compatibility with standard manufacturing processes. This multi-functionality reduces the need for additional separate structures or processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The MST technology significantly enhances charge carrier mobility by reducing scattering effects and improving interface quality, leading to improved performance in semiconductor devices.
Implementation Method 1
The introduction of an enhanced semiconductor superlattice, referred to as MST technology, which incorporates alternating layers of semiconductor and non-semiconductor materials to reduce effective mass of charge carriers
Implementation Method 2
act as a barrier to dopant diffusion
Data Source
AI summary
A method for making a semiconductor device may include forming spaced apart gate stacks on a substrate with adjacent gate stacks defining a respective trench therebetween. Each gate stack may include alternating layers of first and second semiconductor materials, with the layers of the second semiconductor material defining nanostructures. The method may further include forming respective source/drain regions within the trenches, respective insulating regions adjacent lateral ends of the layers of the first semiconductor material, and respective conductive contact liners in the trenches.


