Connector Via Structures Through Nanostructures for Backside Interconnects
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Solution Overview
Problem
Integration of backside interconnect structures with gate-all-around field effect transistors poses a challenge due to the need for patterned structures to be etched through at the level of gate-all-around field effect transistors, leading to high electrical resistance and voltage drop in signal transmission.
Innovation Solution
The development of low resistance connection via structures through device-level structures within a device structure, including semiconductor nanostructures, which reduce electrical resistance between GAA field effect transistors and backside metal interconnect structures by forming a conductive path using connector via structures that extend through the device level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If patterned structures are etched through at the level of gate-all-around field effect transistors to integrate backside interconnect structures, then device density and packaging capability are improved, but electrical resistance and voltage drop increase
Solution Approach 1:
The patent transitions from planar 2D interconnect structures to 3D vertical interconnect structures by forming connector vias that extend through the device level. This dimensional change allows backside interconnect structures to be integrated without requiring patterned etching at the gate level, thereby maintaining low electrical resistance while achieving high device density.
Solution Approach 2:
The patent introduces connector vias as intermediary structures that bridge the front-side device level and backside interconnect level. These vias serve as conductive pathways that reduce electrical resistance by providing direct vertical connections, eliminating the need for high-resistance patterned structures at the gate-all-around transistor level.
2Reliability
If connector via structures are formed to extend through the device level, then electrical resistance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming the connector vias and filling them with conductive material before finalizing the backside interconnect structure integration. This preliminary formation of conductive pathways simplifies subsequent manufacturing steps and reduces overall process complexity despite the added vertical dimension.
Solution Approach 2:
The patent segments the interconnect structure into distinct functional components: front-side device level, connector vias extending through the device level, and backside interconnect level. This segmentation allows each component to be optimized and manufactured independently, reducing overall manufacturing complexity while maintaining low electrical resistance.
Data Source
AI summary
A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. Recess cavities are formed to expose a first active region and the epitaxial semiconductor material portion. A metallic cap structure is formed on the first active region, and a sacrificial metallic material portion is formed on the epitaxial semiconductor material portion. A connector via cavity is formed by anisotropically etching the sacrificial metallic material portion and an underlying portion of the epitaxial semiconductor material portion while the metallic cap structure is masked with a hard mask layer. A connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.