Nanostructured Channel Layout for Equipotential GAA FETs
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Solution Overview
Problem
The scaling down of semiconductor devices leads to increased complexity and variability in channel dimensions, resulting in variations in electrical potential and device parameters such as threshold voltage, drain induced barrier lowering, and current density across different FETs, which affects performance and reliability.
Innovation Solution
Incorporating nanostructured vertical channel regions within a stack of nanostructured horizontal channel regions in gate-all-around FETs, where the nanostructured vertical channel provides an electrical connection between the horizontal channel regions, ensuring equipotential distribution of electrical potential and mitigating dimension-related variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are scaled down to increase storage capacity and processing speed, then device performance and storage capacity are improved, but manufacturing complexity and dimension variability increase
Solution Approach 1:
The patent implements a nested channel structure where vertical channel regions are positioned within or between horizontal channel regions, creating a three-dimensional nested architecture. This nesting approach increases the effective channel volume and transistor density without proportionally increasing manufacturing complexity, as both channel orientations can be formed using sequential epitaxial growth processes.
Solution Approach 2:
The patent transitions from two-dimensional planar channels to three-dimensional channels by introducing vertical channel regions in addition to horizontal channels. This dimensional expansion increases the channel volume and carrier transport pathways, improving device performance while the vertical-horizontal integration is achieved through controlled epitaxial growth that manages manufacturing complexity.
2Productivity
If channel dimensions are reduced to increase device density, then device density is improved, but parameter variability across devices increases
Solution Approach 1:
The patent creates distinct local channel regions with different orientations (horizontal and vertical) that can be independently optimized. Each channel region maintains controlled dimensions through localized epitaxial growth, allowing the device to achieve high density while reducing parameter variability by having multiple channels with consistent local properties rather than relying on a single critical dimension.
Solution Approach 2:
The patent forms composite channel structures using different semiconductor materials (e.g., Si/SiGe superlattices) with distinct crystalline orientations. These composite materials enable the formation of both horizontal and vertical channels with controlled dimensions through material-specific growth rates and orientations, achieving high device density while maintaining manufacturing precision through material-driven dimensional control.
3Reliability
If vertical channel regions are added to horizontal channel regions, then current density and electrical potential distribution are improved, but device structure complexity increases
Solution Approach 1:
The patent segments the channel function into distinct horizontal and vertical channel regions, each performing specific electrical transport functions. The vertical channels provide equipotential pathways that complement the horizontal current flow, improving electrical potential distribution. This segmentation is achieved through separate epitaxial growth steps, managing structure complexity through process modularity.
Solution Approach 2:
The patent creates a multi-functional channel structure where both horizontal and vertical channels serve electrical transport functions simultaneously. The vertical channels provide equipotential distribution while horizontal channels provide current flow pathways, creating a universal channel architecture that performs multiple electrical functions within an integrated structure formed through sequential epitaxial processes.
Data Source
AI summary
A semiconductor device with different configurations of nanostructured channel regions and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a fin structure disposed on a substrate, a stack of nanostructured horizontal channel (NHC) regions disposed on the fin structure, a nanostructured vertical channel (NVC) region disposed within the stack of NHC regions, a source/drain (S/D) region disposed on the fin structure, and a gate structure disposed on the NHC regions and on portions of the NVC region that are not covered by the NHC regions and the fin structure.