Nanostructured Channel Layout With Vertical Link for Variability Control
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down semiconductor devices while maintaining performance and reducing variability due to dimension variations in nanostructured channel regions.
Innovation Solution
The introduction of nanostructured vertical channel (NVC) regions within a stack of nanostructured horizontal channel (NHC) regions in gate-all-around (GAA) FETs, which provides electrical connection between NHC regions and ensures equal distribution of electrical potential, mitigating dimension-related variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are scaled down to increase storage capacity and processing speed, then device performance and storage capacity are improved, but manufacturing complexity and parameter variability increase
Solution Approach 1:
The channel region is segmented into multiple stacked nanosheets (first, second, third nanosheets) with different semiconductor materials. This segmentation allows each nanosheet to contribute differently to device performance, enabling higher effective channel width and improved current drive without proportionally increasing manufacturing complexity, as the stacked structure can be formed through sequential deposition processes.
Solution Approach 2:
Different nanosheets are assigned different semiconductor materials (e.g., SiGe, Si, SiC) with specific properties optimized for their functional roles. The first and third nanosheets use materials with higher hole mobility for channel conduction, while the second nanosheet uses material with lower hole mobility to act as a barrier. This local quality differentiation improves device performance while maintaining manageable manufacturing complexity through targeted material selection.
2Speed
If device dimensions are reduced to improve performance, then processing speed increases, but dimension variations cause increased parameter variability
Solution Approach 1:
The channel structure uses composite materials with different bandgaps and hole mobilities arranged in a stacked configuration. The combination of SiGe, Si, and SiC nanosheets creates a composite channel that achieves higher effective width and improved current drive while the varied material properties help mitigate the impact of dimensional variations through material property compensation.
3Power
If nanostructured channel regions are used to improve device performance, then current density increases, but intra-device and inter-device parameter variability increases
Solution Approach 1:
The gate structure completely surrounds each nanosheet channel region, creating gate-all-around contact that establishes equipotential conditions across the channel width. This equipotential configuration ensures uniform electric field distribution and consistent carrier injection across all nanosheets, reducing intra-device parameter variability while maintaining high current density through the stacked structure.
Data Source
AI summary
A semiconductor device with different configurations of nanostructured channel regions and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a fin structure disposed on a substrate, a stack of nanostructured horizontal channel (NHC) regions disposed on the fin structure, a nanostructured vertical channel (NVC) region disposed within the stack of NHC regions, a source/drain (S/D) region disposed on the fin structure, and a gate structure disposed on the NHC regions and on portions of the NVC region that are not covered by the NHC regions and the fin structure.