Nanostructured Chip Stress Dispersion via Nanopillar Segmentation
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Solution Overview
Problem
Conventional wafer manufacturing processes face issues with stress generation due to differing thermal expansion coefficients and lattice constants between substrates and epitaxial layers, leading to cracks, bowings, and fragmentation, resulting in low yield and processing challenges.
Innovation Solution
A nanostructured chip is produced with a substrate and a nanostructured layer formed on its second surface, which disperses stress by forming nanopillars on the substrate's surface, increasing flexural strength and preventing cracks or fragmentation in the epitaxial layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an epitaxial layer is formed on a substrate with different material composition, then the functional performance of the chip is improved, but stress is generated due to different thermal expansion coefficients, leading to cracks and bowings
Solution Approach 1:
The substrate surface is segmented into a nanostructured layer with nanopillars, creating a hierarchical structure that divides the stress distribution. This segmentation allows the epitaxial layer to be formed while the nanostructured substrate disperses the thermal stress through its distributed pillar architecture, preventing crack formation.
Solution Approach 2:
The invention creates a composite structure combining the substrate material with a nanostructured layer of different morphology (nanopillars). This composite architecture at the nanoscale provides both the mechanical support needed for epitaxial layer formation and the stress-dispersing characteristics to prevent thermal mismatch damage.
2Adaptability or versatility
If the lattice constants of substrate and epitaxial layer are mismatched, then different material properties are achieved, but stress is generated causing cracks or wafer fragmentation
Solution Approach 1:
The nanostructured layer segments the lattice mismatch stress into numerous small stress fields distributed across the nanopillar array. This segmentation prevents the accumulation of critical stress that would lead to wafer fragmentation, allowing materials with different lattice constants to be combined successfully.
Solution Approach 2:
The nanostructured layer introduces local structural variations at the nanoscale, creating regions with different mechanical properties. This local quality variation allows the structure to accommodate lattice mismatch locally while maintaining overall wafer integrity and enabling the use of materials with different material properties.
3Ease of manufacture
If a conventional substrate is used without nanostructuring, then the manufacturing process is simple, but the flexural strength is insufficient to prevent cracks during cooling
Solution Approach 1:
The nanostructured layer is formed on the substrate before the epitaxial layer is deposited. This preliminary action prepares the substrate surface with stress-dispersing characteristics in advance, ensuring that when the epitaxial layer is formed and thermal stress occurs during cooling, the structure is already equipped to handle the stress without cracking.
Solution Approach 2:
The invention changes the physical parameters of the substrate surface by creating a nanostructured morphology with nanopillars. This parameter change at the nanoscale (from flat to structured surface) dramatically increases the flexural strength and stress tolerance while maintaining compatibility with existing manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The nanostructured layer effectively disperses stress, enhancing the flexural strength of the nanostructured chip, preventing cracks and fragmentation, and improving processing outcomes by matching thermal expansion coefficients and lattice constants.
Implementation Method 1
the nanostructured layer effectively disperses the stress in the nanostructured chip to increase the flexural strength of the nanostructured chip
Implementation Method 2
matching thermal expansion coefficients and lattice constants
Data Source
AI summary
A nanostructured chip includes a substrate and a nanostructured layer, wherein the substrate has a first surface and a second surface on which the nanostructured layer is formed. A method of producing the nanostructured chip includes the step of forming the nanostructured layer on the second surface of the substrate. Whereby, the nanostructured layer effectively disperses a stress to increase the flexural strength of the nanostructured chip. Therefore, during the subsequent procedures to form an epitaxial layer on the first surface, the nanostructured layer is helpful to prevent the epitaxial layer from generating cracks, and prevent the substrate from bowings, or fragments.