3D Nanostructured MIM Capacitor for High-Density Packaging

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current discrete metal-insulator-metal (MIM) capacitors face challenges in miniaturization due to parasitic capacitances, material limitations, and cost constraints, making them unsuitable for compact electronic devices and power management systems, especially in 2D and 3D packaging where space and cost efficiency are critical.

Innovation Solution

A discrete MIM energy storage component is developed using a MIM-arrangement with vertically grown conductive nanostructures, a conduction controlling material, and a second electrode layer that fills the space between nanostructures, embedded in an electrically insulating encapsulation material, allowing for high capacitance density and reduced profile height, suitable for 2D and 3D packaging with improved reliability and cost-effectiveness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If traditional planar MIM capacitor structures are used, then manufacturing is simple, but capacitance density is low and parasitic capacitances are high

Engineering Contradiction:
Improvecapacitance densityVSAvoidstructure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent transitions from planar 2D capacitor structures to vertically oriented 3D nanostructures (nanowires, nanotubes, nanofibers) that grow perpendicular to the substrate. This dimensional change enables significantly higher capacitance density by increasing the effective electrode surface area within the same footprint while maintaining manufacturing feasibility through vertical growth processes

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent employs porous or high-surface-area nanostructures such as nanowires, nanotubes, and nanofibers as electrodes. These structures provide dramatically increased surface area for charge storage compared to planar electrodes, directly enhancing capacitance density while the vertical orientation and controlled morphology help minimize parasitic capacitances from field oxide

Inventive Principle:
Principle #31Porous materials

2Manufacturing precision

If vertically grown nanostructures are used to increase capacitance density, then capacitance per area improves, but parasitic capacitances from field oxide and random growth increase

Engineering Contradiction:
Improvecapacitance densityVSAvoidparasitic capacitance
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The patent applies local quality by providing conformal dielectric coating only where needed - specifically coating the vertical nanostructures and selectively leaving areas free of field oxide. This localized approach ensures that dielectric material is present at the high-field regions around nanostructures for capacitance enhancement while minimizing dielectric presence in regions that would create parasitic capacitances

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent converts the potential harm of random nanostructure growth outside device areas into a benefit by implementing selective area growth techniques. The field oxide that would normally create parasitic capacitances is instead used as a natural barrier to confine nanostructure growth to designated device regions, thereby eliminating the source of parasitic effects while maintaining the high capacitance density benefits of vertical growth

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

3Reliability

If discrete capacitors are placed on circuit boards, then power management is achieved, but board area and mass fraction increase

Engineering Contradiction:
Improvepower managementVSAvoidboard area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent enables nesting of high-capacitance MIM energy storage components directly within or alongside semiconductor devices at the wafer level. This nested integration allows capacitors to be embedded in the same package or substrate as the active circuitry, dramatically reducing the overall board area and mass fraction occupied by power management components while maintaining effective power management functionality

Inventive Principle:
Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enables compact, high-capacitance, and reliable energy storage components with reduced parasitic effects, suitable for 2D and 3D packaging, offering improved performance and cost-effectiveness, while maintaining stability against temperature and voltage variations.

Implementation Method 1

metal-insulator-metal (MIM) electrostatic and/or electrochemical energy storage components, including capacitors and batteries

Methodology Applied
Scientific EffectElectrostatic energy storage: Capacitance

Implementation Method 2

metal-insulator-metal (MIM) electrostatic and/or electrochemical energy storage components, including capacitors and batteries

Methodology Applied
Scientific EffectElectrochemical energy storage: Battery (electricity)

Data Source

PatentUS12033797B2Discrete metal-insulator-metal (MIM) energy storage component and manufacturing method
Publication Date: 2024.07.09 SMOLTEK AB
  • US12033797B2 patent drawing
  • US12033797B2 patent drawing
  • US12033797B2 patent drawing

AI summary

A discrete metal-insulator-metal (MIM) energy storage component, the energy storage component comprising: a MIM-arrangement comprising: a first electrode layer; a plurality of conductive nanostructures grown from the first electrode layer; a conduction controlling material covering each nanostructure in the plurality of conductive nanostructures and the first electrode layer uncovered by the conductive nanostructures; and a second electrode layer covering the conduction controlling material; a first connecting structure for external electrical connection of the capacitor component; a second connecting structure for external electrical connection of the capacitor component; and an electrically insulating encapsulation material at least partly embedding the MIM-arrangement.