Nanostructure Transistor Air-Gap Gate Spacing for Lower Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices shrink in size, increased capacitance between the source/drain region and the gate structure of nanostructure transistors leads to reduced performance due to longer switching times and increased resistance-capacitance time constants, exacerbated by short channel effects and source/drain electron tunneling.
Innovation Solution
The inner spacers between the source/drain region and sacrificial nanostructure layers are removed, and the sacrificial layers are replaced with a gate structure, creating air gaps with a lower dielectric constant to reduce capacitance, using a porous interfacial layer to prevent filling with gate material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If inner spacers are present between source/drain region and gate structure, then structural support and alignment are provided, but capacitance increases leading to longer switching times
Solution Approach 1:
The inner spacers are selectively removed from between the source/drain region and the gate structure after the gate structure is formed. This extraction eliminates the capacitive coupling between these components, reducing the RC time constant and enabling faster switching speeds while maintaining the necessary structural integrity through alternative support mechanisms
Solution Approach 2:
The gate structure is formed around the inner spacers before their removal. This preliminary formation ensures proper alignment and structural support during critical processing steps, and allows the gate structure to serve as a template for subsequent spacer removal and air gap formation
2Reliability
If gate structure is formed around sacrificial layers, then gate-all-around control is achieved, but inner spacers may be damaged or misaligned
Solution Approach 1:
The gate structure is formed in advance around the inner spacers and sacrificial layers, using the inner spacers as temporary placeholders that define the precise location where the gate should wrap around. This preliminary action ensures accurate gate-all-around alignment while protecting the inner spacers from damage during gate formation processing
Solution Approach 2:
The inner spacers serve as intermediary structures during the gate formation process, providing a physical reference and protective barrier that enables precise gate-all-around alignment. After the gate structure is successfully formed, the inner spacers are removed as they have fulfilled their intermediary function
3Productivity
If technology node size is reduced, then device density increases, but short channel effects and electron tunneling increase
Solution Approach 1:
The inner spacers are removed to eliminate parasitic capacitance between the source/drain region and gate structure, which becomes increasingly significant at smaller technology nodes. This extraction reduces the RC time constant and mitigates the impact of short channel effects, enabling reliable operation at higher device densities
Solution Approach 2:
The dielectric environment between the source/drain region and gate structure is changed from a solid spacer material to air (vacuum), which has a lower dielectric constant. This parameter change reduces capacitance and helps counteract the increased short channel effects and electron tunneling that occur at smaller technology node dimensions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces capacitance and enhances switching speed by minimizing the dielectric constant in the gaps, leading to faster transistor operation and reduced short channel effects.
Implementation Method 1
The dielectric constant (or relative permittivity) of the air gaps between the source/drain region and the gate structure is less than the dielectric constant of the material of the inner spacers. The lesser dielectric constant of the air gaps reduces the amount of capacitance between the source/drain region and the gate structure.
Data Source
AI summary
Inner spacers between a source/drain region of a nanostructure transistor and sacrificial nanostructure layers of the nanostructure transistor are removed prior to formation of a gate structure of the nanostructure transistor. The sacrificial nanostructure layers are removed, and then the inner spacers are removed. The sacrificial nanostructure layers are then replaced with the gate structure of the nanostructure transistor such that the gate structure and the source/drain region are spaced apart by air gaps that result from the removal of the inner spacers. The dielectric constant (or relative permittivity) of the air gaps between the source/drain region and the gate structure is less than the dielectric constant of the material of the inner spacers. The lesser dielectric constant of the air gaps reduces the amount of capacitance between the source/drain region and the gate structure.