Nonvolatile Nanotube Diodes for High-Density 3D Memory

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Solution Overview

Problem

The semiconductor industry faces challenges in developing denser memory technologies that reduce chip area while maintaining memory efficiency and cost-effectiveness, as existing solutions like 3-D EPROM arrays are limited to one-time programmable memories and require significant lithographic and process changes, which are not scalable for larger memory functions.

Innovation Solution

The development of nonvolatile nanotube diodes and nanotube blocks that utilize nanotube switching elements to create conductive pathways between terminals in response to electrical stimuli, enabling multiple logic states and scalable memory architectures, integrated into dense 3-D memory arrays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If 3-D EPROM arrays are used to achieve higher memory density, then memory capacity increases, but the memory becomes one-time programmable and requires significant lithographic and process changes

Engineering Contradiction:
Improvememory capacityVSAvoidprogrammability
Core Design Contradiction:
Quantity of substanceVSAdaptability or versatility

Solution Approach 1:

The patent uses phase change material (such as GST - germanium antimony telluride) that can reversibly change between crystalline and amorphous phases. By controlling the phase state through electrical stimulation, the memory can be programmed and erased multiple times, providing rewritable capability while maintaining high density 3-D architecture

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The invention employs composite structures combining phase change material with nanotube switching elements and diode structures. This composite approach enables multiple logic states through different resistance levels, achieving both high capacity and reprogrammability in a single cell

Inventive Principle:
Principle #40Composite materials

2Quantity of substance

If 3-D EPROM arrays are used to achieve higher memory density, then memory capacity increases, but significant lithographic and process changes are required

Engineering Contradiction:
Improvememory capacityVSAvoidlithographic and process complexity
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

The patent designs the memory cell to be compatible with existing CMOS fabrication processes. The phase change material can be deposited using standard sputtering or evaporation techniques, and the nanotube switching elements can be integrated into existing CMOS lines, allowing the high-density 3-D structure to be manufactured using conventional processes without requiring new lithographic capabilities

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If nanotube switching elements are used to create conductive pathways, then multiple logic states are enabled, but device complexity increases

Engineering Contradiction:
Improvelogic statesVSAvoidnanotube switching structure
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent combines the phase change material, nanotube switching element, and diode structures into a single integrated memory cell. The nanotube switching element controls current flow to the phase change material, and the diode structure enables selective addressing. This merging of multiple functions into one compact cell achieves multiple logic states without proportionally increasing overall device complexity

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for the creation of high-density memory arrays that can write logic states multiple times, reducing chip area and improving memory efficiency, while being compatible with existing CMOS processes, enabling stand-alone and embedded logic functions.

Implementation Method 1

a nanotube switching element including a nanotube fabric article in electrical communication with the semiconductive element, the nanotube fabric article disposed between and capable of forming a conductive pathway between the semiconductor element and the second terminal

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS9287356B2Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same
Publication Date: 2016.03.15 NANTERO INC
  • US9287356B2 patent drawing
  • US9287356B2 patent drawing
  • US9287356B2 patent drawing

AI summary

A non-volatile nanotube switch and memory arrays constructed from these switches are disclosed. A non-volatile nanotube switch includes a conductive terminal and a nanoscopic element stack having a plurality of nanoscopic elements arranged in direct electrical contact, a first comprising a nanotube fabric and a second comprising a carbon material, a portion of the nanoscopic element stack in electrical contact with the conductive terminal. Control circuitry is provided in electrical communication with and for applying electrical stimulus to the conductive terminal and to at least a portion of the nanoscopic element stack. At least one of the nanoscopic elements is capable of switching among a plurality of electronic states in response to a corresponding electrical stimuli applied by the control circuitry to the conductive terminal and the portion of the nanoscopic element stack. For each electronic state, the nanoscopic element stack provides an electrical pathway of corresponding resistance.