Nanowire Alignment via Optical Lithography Markers
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Solution Overview
Problem
Current methods for aligning nanowires on insulating substrates are difficult to scale industrially due to challenges in achieving parallel alignment and contacting individual nanowires with metal electrodes, particularly for transistor applications, as existing techniques require complex and costly lithography processes.
Innovation Solution
A method using coarse optical lithography to create nanowires on a substrate with arbitrary orientation, followed by a novel alignment process to align them parallel to the substrate, allowing for electrical contacting with circular and ring-shaped electrodes, enabling cost-effective and scalable production of nanowire transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If nanowires are transferred using electrophoresis or microfluidics to achieve alignment, then nanowire positioning is improved, but device complexity and manufacturing cost increase significantly
Solution Approach 1:
The alignment process is segmented into two independent stages: (1) nanowire growth with arbitrary orientation on the substrate, and (2) subsequent alignment of nanowire ends using a alignment marker and lithography. This segmentation allows each stage to be optimized independently, avoiding the need for complex integrated alignment systems.
Solution Approach 2:
Alignment markers are deposited on the substrate before nanowire growth. These pre-placed markers serve as reference points that guide the subsequent alignment process, enabling precise positioning without requiring complex real-time alignment systems during nanowire placement.
2Manufacturing precision
If electron beam lithography is used for contacting individual nanowires, then contacting precision is improved, but manufacturing cost and processing time increase
Solution Approach 1:
The invention replaces expensive electron beam lithography with conventional optical lithography for electrode patterning. Optical lithography uses cheaper, more accessible equipment and materials, making the process economically viable for industrial parallel manufacturing while achieving sufficient precision for nanowire contacting.
Solution Approach 2:
The alignment markers serve multiple functions: they guide nanowire alignment, define electrode positions, and enable both nanowire and electrode patterning using the same optical lithography system. This multi-functionality eliminates the need for separate high-precision alignment systems.
3Adaptability or versatility
If nanowires are grown with arbitrary orientation, then growth flexibility is improved, but alignment difficulty increases
Solution Approach 1:
Instead of attempting to grow nanowires in a specific orientation from the beginning, the invention inverts the approach: nanowires are grown with arbitrary orientation, and then the alignment is achieved by positioning the electrodes relative to the grown nanowires using alignment markers as references. This inversion simplifies the growth process while maintaining alignment precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for cost-effective, parallel production of nanowire transistors without the need for expensive electron beam lithography, enabling industrial-scale manufacturing of nanowire sensors with high sensitivity.
Implementation Method 1
catalytically active metal nanoparticles with a diameter in the range of 0.5-50 nm are deposited on locally defined nucleation surfaces
Implementation Method 2
the surface and the metal nanoparticles deposited on it are exposed to a gas stream containing at least one gaseous silicon component, with at least one nanowire protruding from the substrate being formed
Data Source
Figure 1a~1d2
Figure 2a~2d
Figure 3a~3c1
AI summary
The invention relates, inter alia, to a method for producing a conductor structure, comprising at least one silicon nanowire (4) having a diameter of less than 50 nm, which nanowire is contacted via at least two points by electrodes (11, 13, 30), and wherein the at least one nanowire (4) and the electrodes (11, 13, 30) are arranged on one plane on a substrate (1, 5), which is characterized in that a) catalytically active metal nanoparticles having a diameter in the range of 0.5-50 nm are deposited on the surface (2) of an insulating substrate (1), b) the surface and the metal nanoparticles deposited thereon are exposed to a gas flow containing at least one gaseous silicon component at a temperature in the range of 300-1100 ºC and during a time period in the range of 10-200 minutes, wherein at least one nanowire (4) of a length in the range of 5-200 µm projecting from the substrate is formed, c) said at least one nanowire (4) projecting from the surface of the substrate (1) is deposited in one plane with one of the contact surfaces (6) corresponding to the surface (2) of the insulating substrate (1) by applying a secondary substrate (5), and d) either the at least one nanowire (4) deposited on the insulating substrate (1) is contacted at two different points by electrodes (11, 13, 30) or the at least one nanowire adhering to the secondary substrate (5) is contacted at two different points by electrodes (11, 13, 30).