Nanowire Array Hard Mask for Planar Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of nanopillar arrays into semiconductor products is hindered by significant topological features and relief issues, such as cavities and misoriented pores, which complicate subsequent manufacturing steps and contact formation.
Innovation Solution
A level-sustaining hard mask is used to cover the peripheral region of the nanopillar array, preventing the formation of large topological features by exposing only the nanopillars inwardly of the peripheral region, thereby facilitating integration into integrated circuits and reducing strain on the mask.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If nanopillar arrays are integrated into semiconductor products using conventional methods, then high capacitance density can be achieved, but significant topological features and relief issues occur that complicate subsequent manufacturing steps
Solution Approach 1:
A hard mask is formed over the nanopillar array structure before subsequent manufacturing steps. This preliminary action prevents the formation of large topological features by maintaining a planar surface during anodization and processing, thereby simplifying integration into semiconductor products while preserving high capacitance density
Solution Approach 2:
The hard mask acts as an intermediary layer between the nanopillar array and subsequent processing steps. It mediates the conflict between achieving high capacitance density through nanopillar structures and avoiding topological complexity, by providing a planarizing effect that enables smooth integration into integrated circuits
2Ease of manufacture
If nanopillar arrays are formed without a level-sustaining hard mask, then manufacturing simplicity is maintained, but large topological features and cavities form that hinder integration
Solution Approach 1:
The hard mask is applied in advance before anodization and subsequent steps. This preliminary action sustains the surface level and prevents cavity formation, thereby improving integration precision without significantly complicating the manufacturing process
Solution Approach 2:
The introduction of the hard mask changes the surface topology parameter from uneven to planar. This parameter change enables precise integration into semiconductor products by preventing the formation of large topological features while maintaining ease of manufacture through a straightforward additional step
3Device complexity
If the hard mask covers the entire nanopillar array, then topological features are minimized, but strain on the mask increases
Solution Approach 1:
The hard mask is selectively positioned to cover only specific regions of the nanopillar array where topological feature formation is most problematic. This local quality approach minimizes topological features while reducing the overall area under the mask, thereby decreasing strain and improving mask strength
Solution Approach 2:
By applying the hard mask only where needed rather than uniformly across the entire array, the solution locally addresses topological issues without subjecting the entire mask structure to excessive strain, thus maintaining both low topological complexity and high mask strength
4Device complexity
If nanopillar arrays are released without surrounding porous material, then integration smoothness is improved, but structural support is reduced
Solution Approach 1:
The released nanopillar array is nested within a well structure formed in the substrate. This nesting approach provides structural support through the well walls while maintaining smooth integration at the surface level, as the hard mask covers the peripheral region and creates a planar interface with surrounding structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes topological features, allowing for smoother integration of nanopillar arrays into semiconductor products and integrated circuits, enhancing the continuity of layers and preventing discontinuities in interconnections.
Implementation Method 1
A level-sustaining hard mask is used to cover the peripheral region of the nanopillar array, preventing the formation of large topological features
Implementation Method 2
an array of nanopillars located in the well and extending in a direction from the well floor towards the well mouth
Data Source
AI summary
A nanowire array structure having an array of nanopillars located in a well in a material layer. The nanopillars of the array extend in the direction from the well floor towards the well mouth. A hard mask overlies the outer peripheral nanopillars in the array and extends outwards to cover the remainder of the well mouth. An aperture in the hard mask exposes the nanopillars disposed inwardly of the outer peripheral nanopillars. The hard mask planarizes the structure, avoiding formation of large topological features at the periphery of the array of nanopillars, thus facilitating integration of the structure into a semiconductor product. At least some of the outer peripheral nanopillars may be in pores of anodic oxide. There are also disclosed semiconductor products incorporating such nanowire array structures and methods of their fabrication.