Backside Self-Aligned Source/Drain Contacts in Nanowire IC Structures
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Solution Overview
Problem
The challenge in integrated circuit fabrication lies in achieving backside self-aligned conductive source or drain contacts, particularly for multi-gate and nanowire transistors, where conventional lithographic processes face limitations in scaling and spacing, leading to increased defect density and variability.
Innovation Solution
A method involving a fully self-aligned, mask-less process on the backside of the wafer to form conductive source or drain contacts, which includes recessing sub-fins to form cavities, depositing spacers, and epitaxially growing source or drain structures adjacent to nanowires, followed by metal deposition and planarization, allowing for contact formation without extending to the front-side.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic processes are used to pattern features in semiconductor stacks, then the critical dimension can be reduced to enable scaling, but the spacing between features increases leading to increased defect density and variability
Solution Approach 1:
The patent implements self-aligned contact formation by utilizing the vertical dimension and sidewall spacers to define contact positions, rather than relying solely on planar lithographic patterning. This approach allows contact alignment to be determined by the intersection of the spacer sidewalls with the channel region, enabling precise positioning without increasing lateral spacing requirements
Solution Approach 2:
The sidewall spacers serve a dual function: they act as etch masks during contact hole formation and simultaneously define the precise location of the contacts through self-alignment with the channel region. This self-aligned approach eliminates the need for separate alignment steps and reduces variability associated with conventional multi-step lithographic processes
2Productivity
If multi-gate and nanowire transistors are scaled to smaller dimensions to increase device density, then capacity increases, but maintaining mobility improvement and short channel control becomes increasingly challenging
Solution Approach 1:
The patent applies different material compositions and structural configurations to specific regions of the transistor: silicon germanium is used for the channel region to enhance carrier mobility, while the gate structure and contact regions are optimized independently. This localized optimization allows each region to be tuned for its specific function without compromising overall device performance
Solution Approach 2:
The transistor structure employs composite materials including silicon germanium for the channel, various dielectric materials for isolation and gate insulation, and metallic materials for contacts and interconnects. This multi-material approach enables simultaneous optimization of mobility, short channel control, and electrical characteristics
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces defect density, enables straightforward lithography and etch processes, and provides contact self-alignment, thereby improving device performance and reducing variability in sub-10 nanometer technology nodes.
Implementation Method 1
depositing spacers
Implementation Method 2
depositing spacers
Implementation Method 3
epitaxially growing source or drain structures adjacent to nanowires
Data Source
AI summary
Integrated circuit structures having backside self-aligned conductive source or drain contacts, and methods of fabricating integrated circuit structures having backside self-aligned conductive source or drain contacts, are described. For example, an integrated circuit structure includes a sub-fin structure over a vertical stack of horizontal nanowires. An epitaxial source or drain structure is laterally adjacent and coupled to the vertical stack of horizontal nanowires. A conductive source or drain contact is laterally adjacent to the sub-fin structure and is on and in contact with the epitaxial source or drain structure. The conductive source or drain contact does not extend around the epitaxial source or drain structure.