Backside Source-Drain Access in Nanowire ICs for Power Routing
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Solution Overview
Problem
The scaling of multi-gate transistors in integrated circuits faces challenges due to variability in conventional fabrication processes, limiting further miniaturization beyond the 10 nanometer node, necessitating new methodologies for efficient power delivery and contact access in tight spaces.
Innovation Solution
The implementation of backside source or drain contact differentiated access features, allowing for self-aligned power delivery networks that reduce power network resistance and enable more compact integrated circuit designs by eliminating the need for front-side power delivery, thereby improving performance and reducing manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling multi-gate transistors, then manufacturing compatibility and cost are maintained, but manufacturing precision and reliability deteriorate at 10 nanometer node and below
Solution Approach 1:
The patent inverts the conventional power delivery approach by implementing backside power delivery instead of front-side power delivery. This inversion allows for differentiated access to source and drain contacts from the backside of the substrate, enabling self-aligned power delivery networks that achieve the required manufacturing precision at 10nm node and below while maintaining compatibility with existing bulk silicon substrate infrastructure.
Solution Approach 2:
The patent transitions from two-dimensional front-side power delivery to three-dimensional backside power delivery. By utilizing the vertical dimension and accessing contacts from the backside of the substrate, the invention creates self-aligned power delivery networks that improve manufacturing precision without compromising ease of manufacture, as the backside access provides natural alignment references.
2Area of stationary object
If front-side power delivery networks are used, then power delivery is achieved, but device complexity and space utilization worsen due to limited real estate
Solution Approach 1:
The patent inverts the power delivery architecture by moving power delivery networks from the front side to the backside of the substrate. This inversion frees up front-side real estate for additional functional units while the backside power delivery networks provide simplified routing and reduced resistance, thereby decreasing device complexity and improving space utilization.
Solution Approach 2:
The patent utilizes the third dimension (backside of substrate) for power delivery networks, effectively adding a new layer for power distribution. This dimensional transition eliminates the need for power networks to compete for space on the front side, increasing available chip area for functional units while simplifying the overall power network structure through self-aligned access.
3Quantity of substance
If transistor dimensions are reduced to increase density, then capacity increases, but power network resistance and manufacturing variability worsen
Solution Approach 1:
The patent inverts the access approach by implementing backside access to source and drain contacts, creating self-aligned power delivery networks. This inversion provides more robust power delivery paths that are less sensitive to dimensional variations, thereby improving power delivery reliability as transistor dimensions are reduced to increase the number of functional units on chip.
Solution Approach 2:
The patent implements self-aligned power delivery networks where the backside access structures automatically align with the source and drain contacts through the substrate thickness. This self-alignment mechanism eliminates the need for additional alignment steps and reduces sensitivity to manufacturing variability, ensuring reliable power delivery even as transistor dimensions are scaled down to pack more functional units.
Data Source
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AI summary
Integrated circuit structures having backside source or drain contact differentiated access are described. In an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure over a first conductive material having a first depth below the first epitaxial source or drain structure. A second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, the second epitaxial source or drain structure over a second conductive material having a second depth below the second epitaxial source or drain structure, the second depth greater than the first depth.