Nanowire Bending for Planar Integration on Si(001) Substrates
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Solution Overview
Problem
Current methods for integrating nanowires into silicon-based electronics face challenges such as random growth directions, complex contacting, and lattice mismatch issues, particularly for III-V materials like InAs on Si substrates, which hinder the development of high-density and efficient tunnel field effect transistors.
Innovation Solution
A method involving the growth and elastic bending of nanowires onto specific facets of a silicon substrate, allowing for lithographic control and separation from the substrate to minimize strain, enabling the formation of complementary tunnel field effect transistors with improved integration density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If nanowires are grown vertically from Si(111) surface, then nanowire growth is achieved, but random growth directions and complex contacting issues arise
Solution Approach 1:
Instead of growing nanowires vertically from the substrate surface (conventional approach), the patent inverts the approach by growing nanowires horizontally along the substrate surface. This is achieved by forming nanowires on sidewalls of sacrificial structures, causing them to grow parallel to the substrate rather than perpendicular to it, thereby eliminating random growth directions and simplifying contacting.
Solution Approach 2:
The patent introduces sacrificial structures (such as silicon dioxide pillars or silicon nitride structures) as intermediary elements. These sacrificial structures serve as templates for nanowire growth and are later removed to release the nanowires. This intermediary approach enables controlled horizontal growth and subsequent planar integration without direct substrate contact during growth.
2Reliability
If III-V nanowires are grown on Si substrates, then high mobility conduction is achieved, but lattice mismatch causes strain and integration issues
Solution Approach 1:
The patent extracts the nanowires from the substrate during processing by removing sacrificial structures. This separation eliminates the lattice mismatch strain between III-V nanowires and Si substrates, as the nanowires are no longer mechanically constrained to the substrate lattice. The nanowires maintain their high mobility properties while being freed from strain-induced defects.
Solution Approach 2:
The patent segments the integration process into distinct phases: growth phase (where nanowires grow on sacrificial structures), release phase (where sacrificial structures are removed), and integration phase (where freed nanowires are positioned on the substrate). This segmentation allows the nanowires to achieve high mobility during growth without substrate strain, then be integrated separately without lattice mismatch constraints.
3Productivity
If nanowires are grown with lithographic positioning, then integration density is improved, but growth control and organization become more difficult
Solution Approach 1:
The patent performs preliminary patterning of sacrificial structures using lithography before nanowire growth. The sacrificial structures are pre-formed at desired locations and orientations, providing predetermined growth sites that guide nanowire placement. This preliminary action enables lithographic positioning control without complicating the actual nanowire growth process, as the growth simply follows the pre-defined sacrificial template.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the controlled growth and integration of nanowires on Si(001) substrates, overcoming random growth and lattice mismatch issues, and enhances the integration density and performance of tunnel field effect transistors, making them compatible with CMOS technology.
Implementation Method 1
elastically bending the at least one nanowire
Data Source
AI summary
Provided is a method for growing a nanowire, including: providing a substrate with a base portion having a first surface and at least one support structure extending above or below the first surface; forming a dielectric coating on the at least one support structure; forming a photoresist coating over the substrate; forming a metal coating over at least a portion of the dielectric coating; removing a portion of the dielectric coating to expose a surface of the at least one support structure; removing a portion of the at least one support structure to form a nanowire growth surface; growing at least one nanowire on the nanowire growth surface of a corresponding one of the at least one support structure, wherein the nanowire comprises a root end attached to the growth surface and an opposing, free end extending from the root end; and elastically bending the at least one nanowire.