Nanowire Bundle Capacitor Structure for High-Aspect-Ratio 3D Capacitance
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Solution Overview
Problem
Current three-dimensional capacitors face limitations in achieving high capacitance per unit volume due to reduced breakdown voltage and structural constraints, particularly in increasing the slenderness ratio of their vertical patterns, which leads to increased manufacturing time and quality issues as the aspect ratio exceeds 30:1.
Innovation Solution
The introduction of a capacitor component utilizing a conductive nanowire bundle with connecting conductive layers and a dielectric film, surrounded by a conductive body, allowing for a higher slenderness ratio and improved manufacturing efficiency by using a nanowire bundle-based structure that can be easily processed into a three-dimensional wafer form.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the slenderness ratio of the vertical pattern is increased to achieve higher integration rate, then the capacitance per unit volume is improved, but the manufacturing time increases exponentially and quality deteriorates when the ratio exceeds 30:1
Solution Approach 1:
The patent replaces the conventional etching method (mechanical/chemical removal process) with a nanowire growth method that utilizes vapor-liquid-solid mechanism. This substitution allows for the formation of high-aspect-ratio nanowire structures without the exponential time penalty and quality degradation associated with traditional etching processes. The nanowires are grown epitaxially on semiconductor substrates, enabling precise control over length and diameter while maintaining structural integrity even at slenderness ratios exceeding 30:1.
2Productivity
If the slenderness ratio is increased beyond 30:1 to achieve higher integration rate, then the capacitance per unit volume is improved, but manufacturing costs increase and yield drastically reduces due to lifted, biased or collapsed patterns
Solution Approach 1:
The patent replaces the conventional etching method with a nanowire growth method that utilizes vapor-liquid-solid mechanism. This substitution allows for the formation of high-aspect-ratio nanowire structures without the exponential time penalty and quality degradation associated with traditional etching processes. The nanowires are grown epitaxially on semiconductor substrates, enabling precise control over length and diameter while maintaining structural integrity even at slenderness ratios exceeding 30:1.
Solution Approach 2:
The patent employs precise control of growth parameters including temperature, pressure, gas flow rates, and precursor ratios during the nanowire formation process. By optimizing these parameters, the method achieves uniform nanowire arrays with controlled density and orientation, preventing defects such as lifted, biased, or collapsed patterns. The growth conditions are carefully tuned to ensure that nanowires maintain their structural integrity throughout the manufacturing process.
3Ease of manufacture
If conventional etching or growth methods are used to manufacture three-dimensional capacitors, then the basic structure is achieved, but the manufacturing time increases exponentially and costs increase for higher slenderness ratios
Solution Approach 1:
The patent replaces the conventional etching method (mechanical/chemical removal process) with a nanowire growth method that utilizes vapor-liquid-solid mechanism. This substitution allows for the formation of high-aspect-ratio nanowire structures without the exponential time penalty and quality degradation associated with traditional etching processes. The nanowires are grown epitaxially on semiconductor substrates, enabling precise control over length and diameter while maintaining structural integrity even at slenderness ratios exceeding 30:1.
Data Source
AI summary
A capacitor component includes: a plurality of conductive nanowires disposed to be spaced apart from each other; first and second connecting conductive layers respectively disposed on one end and the other end of the plurality of conductive nanowires, and connected to the plurality of conductive nanowires; a conductive body surrounding the plurality of conductive nanowires; and a dielectric film disposed between the plurality of conductive nanowires, each of the first and second connecting conductive layers, and the conductive body.


