Nanowire Capacitor Bottom-Up Growth for High Integration Density
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Solution Overview
Problem
Conventional capacitor forming methods for semiconductor devices, such as photolithography and etching, result in increased costs and technical limitations due to high aspect ratio structures required for high integration density, especially for sizes below 20 nm, which is challenging for top-down technologies.
Innovation Solution
The use of nanowires with a pillar shape, a seed layer, and a dielectric film in semiconductor devices, where the nanowires are grown using a bottom-up technique, providing a high aspect ratio capacitor structure at a lower cost and enabling higher integration density without the need for expensive processes like EUV or double patterning technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography and etching processes are used to form capacitors, then manufacturing precision can be maintained for larger dimensions, but manufacturing cost increases and technical limitations arise for high integration density requiring high aspect ratio structures
Solution Approach 1:
The patent inverts the conventional top-down capacitor formation approach by using a bottom-up nanowire growth method. Instead of forming capacitors through photolithography and etching of planar structures, the invention grows nanowires vertically from a seed layer on the capacitor electrode, allowing high aspect ratio structures to form naturally through controlled nanowire epitaxial growth rather than attempting to etch high-sided cavities.
Solution Approach 2:
The patent transitions from two-dimensional planar capacitor structures to three-dimensional vertical nanowire structures. By growing nanowires perpendicular to the substrate surface, the capacitor achieves high aspect ratio and increased effective area without requiring complex multi-step lithography processes, thus reducing manufacturing complexity while maintaining precision.
2Productivity
If high aspect ratio structures are employed to provide sufficient capacitor area for high integration, then integration density improves, but conventional top-down technology results in increased cost due to increased mold height and decreased hole size
Solution Approach 1:
The patent inverts the conventional top-down capacitor formation approach by using a bottom-up nanowire growth method. Instead of forming capacitors through photolithography and etching of planar structures, the invention grows nanowires vertically from a seed layer on the capacitor electrode, allowing high aspect ratio structures to form naturally through controlled nanowire epitaxial growth rather than attempting to etch high-sided cavities.
Solution Approach 2:
The nanowire growth process is self-organizing and self-limiting, where the nanowires grow vertically until they reach a predetermined height or encounter a stopping layer. This self-service mechanism eliminates the need for complex process control to maintain aspect ratio, reducing fabrication complexity and cost while achieving high integration density.
3Area of stationary object
If unit cell size decreases to achieve high integration, then more devices can be packed, but sufficient capacitor area becomes harder to provide with conventional methods
Solution Approach 1:
The patent transitions from two-dimensional planar capacitor structures to three-dimensional vertical nanowire structures. By growing nanowires perpendicular to the substrate surface, the capacitor achieves high aspect ratio and increased effective area without requiring complex multi-step lithography processes, thus reducing manufacturing complexity while maintaining precision.
Solution Approach 2:
The nanowire capacitor structure embeds the capacitor electrode within the nanowire itself, with the dielectric layer conformally coating the nanowire surface and the top electrode forming on the dielectric. This nested configuration maximizes capacitor area within a minimal footprint, enabling high integration density while providing sufficient capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for a semiconductor device with a smaller-sized capacitor and higher integration density while maintaining efficiency, reducing fabrication costs and overcoming technical limitations of conventional methods.
Implementation Method 1
The use of nanowires with a pillar shape, a seed layer, and a dielectric film in semiconductor devices, where the nanowires are grown using a bottom-up technique
Data Source
AI summary
Semiconductor devices and fabricating methods thereof are provided. A semiconductor device may include a substrate, a metal layer on the substrate, a seed layer on the metal layer, a nanowire including a pillar shape on the seed layer, a dielectric film conformally covering the nanowire, and an electrode film on the dielectric film.