Nanowire Transistor Cavity Spacer Alignment Across Channel Widths
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Solution Overview
Problem
Nanowire transistors with different channel widths in integrated circuits face challenges in achieving uniform alignment of cavity spacers with respect to the gate electrode, leading to performance issues such as current leakage and parasitic capacitance due to improper etch processes tailored for specific channel widths.
Innovation Solution
A two-part process for forming gate and cavity spacers, where a first spacer material is deposited over a dummy gate, and after removing the source and drain regions, a second spacer material is deposited to fill cavities between nanowires, with anisotropic etching to expose nanowire ends for epitaxial source/drain formation, ensuring consistent alignment and compositionally different spacer materials for improved alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single spacer material deposition process is used, then the process is simple, but the alignment of cavity spacer with gate electrode is poor
Solution Approach 1:
The spacer formation process is divided into two distinct deposition steps: first depositing a gate spacer material aligned with the gate electrode, then depositing a cavity spacer material to fill cavities between nanowires. This segmentation allows each spacer to be independently optimized for its specific alignment requirements, resolving the contradiction between alignment precision and process complexity.
Solution Approach 2:
The gate spacer is deposited first as a preliminary step before forming the cavity spacer. This preliminary action establishes the reference alignment for the gate electrode, enabling subsequent cavity spacer deposition to be precisely positioned relative to the already-formed gate structure, thereby achieving high alignment precision.
2Ease of manufacture
If sacrificial material is recessed using etch process, then the cavities are formed, but the alignment with gate electrode deteriorates
Solution Approach 1:
The gate spacer is deposited as a preliminary protective and alignment-reference layer before the etch process removes sacrificial material to form cavities. This preliminary action protects the gate electrode during etching and provides a reference for subsequent cavity spacer deposition, maintaining alignment precision despite the aggressive etching required for cavity formation.
Solution Approach 2:
The gate spacer material acts as an intermediary layer between the gate electrode and the cavity spacer. It mediates the alignment relationship, allowing the cavity spacer to be precisely positioned relative to the gate electrode even after sacrificial material removal, thus resolving the alignment deterioration caused by the etch process.
3Manufacturing precision
If uniform spacer material is used across different transistor sizes, then material consistency is maintained, but alignment uniformity across different channel widths is poor
Solution Approach 1:
Different spacer materials are used for different local regions: gate spacer material for regions requiring alignment with the gate electrode, and cavity spacer material for regions requiring cavity filling between nanowires. This local differentiation allows each spacer type to be optimized for its specific function and the varying channel widths of different transistors, achieving alignment uniformity across diverse transistor sizes.
Solution Approach 2:
The invention changes the material parameter of the spacer by using two compositionally different materials. This parameter change enables differential deposition and etching behaviors that can be tuned for different transistor geometries, allowing consistent alignment across transistors with varying channel widths while adapting to local structural requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in reduced parasitic capacitance, minimized leakage, and improved device performance by ensuring uniform spacer alignment across nanowire transistors of varying widths, enhancing overall transistor structure consistency.
Implementation Method 1
depositing a first spacer material to form a gate spacer
Implementation Method 2
depositing a first spacer material to form a gate spacer
Implementation Method 3
The sacrificial material is then recessed using an etch process
Implementation Method 4
depositing a second spacer material in the cavities
Implementation Method 5
depositing a second spacer material in the cavities
Implementation Method 6
A nanowire transistor structure includes a fin on a base... nanowire or nanoribbon instead of a finned channel region
Data Source
AI summary
A transistor structure includes a base and a body over the base. The body comprises a semiconductor material and has a first end portion and a second end portion. A gate structure is wrapped around the body between the first end portion and the second end portion, where the gate structure includes a gate electrode and a dielectric between the gate electrode and the body. A source is in contact with the first end portion and a drain is in contact with the second end portion. A first spacer material is on opposite sides of the gate electrode and above the first end portion. A second spacer material is adjacent the gate structure and under the first end portion of the nanowire body. The second spacer material is below and in contact with a bottom surface of the source and the drain.