Nanowire Channel Structure for 3D Semiconductor Devices
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Solution Overview
Problem
The challenge in semiconductor device manufacturing is to enhance the performance and density of FETs while minimizing the short channel effect, which occurs due to the reduced separation between the source and drain regions, and to achieve this in a cost-effective and reliable manner for both planar and 3D devices like FinFETs.
Innovation Solution
The method involves forming a 3D semiconductor device with a nanowire channel structure by creating trenches in a semiconducting substrate, using selectively etchable materials, and filling them with highly stressed dielectric materials to induce stress in the fins, which improves device performance. This process includes forming a sacrificial gate structure, removing it to define a gate cavity, and selectively etching to create spaces between the semiconducting materials, ultimately forming a gate structure around the nanowires.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the channel length of FETs is significantly decreased to improve switching speed, then the operating speed of FETs is improved, but the separation between source and drain regions is reduced, making it difficult to efficiently inhibit the electrical potential of the source region and channel from being adversely affected by the drain region (short channel effect)
Solution Approach 1:
The patent transitions from planar FET structures to three-dimensional FinFET structures by forming vertically positioned fin-shaped active areas. This dimensional change allows the channel to extend in the vertical dimension while maintaining adequate horizontal separation between source and drain regions, thereby improving switching speed without suffering from short channel effects.
Solution Approach 2:
The gate electrode is segmented into multiple gates that enclose different portions of the fin-shaped active area (front gate, back gate, and potentially side gates). This segmentation allows independent control of different channel regions, enabling better electrostatic control and mitigation of short channel effects while maintaining high switching speed.
2Productivity
If device size is reduced to increase density of FETs on integrated circuit device, then the density of FETs is increased, but the physical size reduction makes it difficult to efficiently inhibit the electrical potential of the source region and channel from being adversely affected by the drain region
Solution Approach 1:
By forming vertically positioned fin-shaped active areas, the patent increases device density in the horizontal plane while the vertical channel provides sufficient electrostatic control to prevent short channel effects. The gate electrode wraps around the fin structure, providing control in multiple directions and maintaining reliability despite reduced planar dimensions.
Solution Approach 2:
The patent employs composite material structures including the fin-shaped active area formed from semiconducting material, surrounded by a gate electrode structure with gate insulation layer. This composite structure enables high density while maintaining proper electrical isolation and control to prevent short channel effects.
3Reliability
If a gate electrode encloses both sides and upper surface of the fin-shaped active area to form a tri-gate structure, then the junction capacitance at the drain region is greatly reduced, but the device complexity increases
Solution Approach 1:
The gate electrode is divided into multiple segmented gates (front gate, back gate, and potentially side gates) that can be formed and controlled independently. This segmentation reduces the complexity of forming a complete wraparound gate by breaking it into manageable sections, while still achieving the tri-gate structure that reduces junction capacitance and mitigates short channel effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces junction capacitance and enhances the performance of 3D semiconductor devices by inducing appropriate stress in the nanowire channel structure, thereby improving switching speed and density while mitigating short channel effects, thus addressing the need for increased performance and reduced manufacturing costs.
Implementation Method 1
filling them with highly stressed dielectric materials to induce stress in the fins
Implementation Method 2
performing at least one etching process to remove the sacrificial gate structure and thereby define a gate cavity
Implementation Method 3
performing at least one selective etching process to selectively remove the first layer of semiconducting material relative to the second layer of semiconducting material within the gate cavity
Data Source
AI summary
One method herein includes forming a plurality of spaced-apart trenches that extend at least partially into a semiconducting substrate, wherein the trenches define a fin structure comprised of first and second layers of semiconducting material, wherein the first layer of semiconducting material is selectively etchable relative to the substrate and the second layer of semiconducting material, forming a sacrificial gate structure above the fin, wherein the gate structure includes a gate insulation layer and a gate electrode, forming a sidewall spacer adjacent the gate structure, performing an etching process to remove the sacrificial gate structure, thereby defining a gate cavity, performing at least one selective etching process to selectively remove the first layer of semiconducting material relative to the second layer of semiconducting material within the gate cavity, thereby defining a space between the second semiconducting material and the substrate, and forming a final gate structure in the gate cavity.