Substrate-less Nanowire Diode Circuits for High-Speed IO
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in scaling multi-gate and nanowire transistors below the 10 nanometer node, where conventional lithographic processes face constraints due to the trade-off between feature dimension and spacing, leading to inefficiencies in current carrying capacity and increased parasitic capacitance in substrate-less nanowire-based lateral diode integrated circuit structures.
Innovation Solution
The solution involves fabricating substrate-less nanowire-based lateral diode integrated circuit structures by retaining SiGe between Si nanowires or using metal gates for heat dissipation, and selectively removing metal gates to reduce capacitance, while maintaining the cross-sectional area for current flow, thereby enhancing current density and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional lithographic processes are used to pattern nanowire transistors at smaller dimensions, then feature size is reduced, but spacing between features increases leading to reduced current carrying capacity
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional nanowire structures with multiple gates wrapping around the channel. This dimensional change allows current to flow through multiple parallel nanowire paths within a compact footprint, effectively increasing current carrying capacity without proportionally increasing the lateral feature spacing
2Reliability
If metal gates are retained in substrate-less nanowire structures, then gate control is improved, but parasitic capacitance increases
Solution Approach 1:
The patent implements selective metal gate retention where metal gates are kept only in regions where strong gate control is critical for device operation, while dielectric gates are used in other regions. This local differentiation optimizes the balance between gate control performance and parasitic capacitance reduction
3Productivity
If feature dimensions are scaled down below 10nm node, then device density is increased, but short channel control and mobility improvement become difficult to maintain
Solution Approach 1:
The patent employs multi-gate structures where outer gates wrap around and control the nanowire channel from multiple directions, creating a nested configuration. This provides superior electrostatic control and short channel effect suppression at sub-10nm dimensions while maintaining high device density through vertical stacking
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for increased current carrying capacity with reduced capacitance and leakage, enabling the construction of high-speed IOs with robust ESD protection and improved performance in dense integrated circuit designs.
Implementation Method 1
retaining SiGe between Si nanowires or using metal gates for heat dissipation
Data Source
AI summary
Substrate-less nanowire-based lateral diode integrated circuit structures, and methods of fabricating substrate-less nanowire-based lateral diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a stack of nanowires. A plurality of P-type epitaxial structures is over the stack of nanowires. A plurality of N-type epitaxial structures is over the stack of nanowires. One or more gate structures is over the stack of nanowires. A semiconductor material is between and in contact with vertically adjacent ones of the stack of nanowires.