Gate-All-Around Nanowire Doping for Voltage Uniformity
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Solution Overview
Problem
Conventional gate-all-around nanowire transistors face challenges with non-uniform turn-on voltage distribution due to non-uniform gate thickness, leading to severe narrow channel effects and performance issues as dimensions decrease.
Innovation Solution
A method involving the formation of a first fin with alternately stacked epitaxial layers on a substrate, where the dielectric layer exposes a channel region with different doping concentrations at the lateral and central surfaces, allowing the second epitaxial layer to form a nanowire after removing the first epitaxial layer, and a gate is formed around the nanowire to adjust the turn-on voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional gate-all-around nanowire transistor is manufactured with uniform doping, then the manufacturing process is simple, but the turn-on voltage is non-uniform due to gate thickness variations
Solution Approach 1:
The patent applies local quality by creating different doping concentrations in different regions of the nanowire channel. Specifically, the channel is divided into a first region and a second region with different doping types or concentrations, allowing each region to compensate for local gate thickness variations and achieve uniform turn-on voltage across the device.
Solution Approach 2:
The patent segments the nanowire channel into multiple doped regions (first region and second region) with different doping characteristics. This segmentation allows independent optimization of each region's electrical properties to compensate for gate thickness non-uniformity, resolving the contradiction between manufacturing simplicity and voltage uniformity.
2Length of moving object
If the channel dimension is decreased to reach lower technology nodes, then the device scaling is achieved, but the narrow channel effect becomes severe
Solution Approach 1:
By implementing different doping concentrations in different channel regions, the patent locally optimizes carrier transport properties. The first doped region and second doped region have tailored doping levels that compensate for quantum confinement and narrow channel effects, maintaining device performance at scaled dimensions.
Solution Approach 2:
The patent changes the doping parameter (concentration and type) across different channel regions to optimize device performance at scaled dimensions. By adjusting doping parameters locally, the patent mitigates narrow channel effects while maintaining the scaled channel geometry required for lower technology nodes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves device performance by allowing for the adjustment of non-uniform turn-on voltage due to gate thickness variations, enhancing carrier mobility and overall device performance.
Implementation Method 1
the dopant diffuses into the surface of the second fin to obtain the first fin
Data Source
AI summary
A gate-all-around nanowire device and a method for forming the gate-all-around nanowire device. A first fin and a dielectric layer on the first fin are formed on a substrate. The first fin includes the at least one first epitaxial layer and the at least one second epitaxial layer that are alternately stacked. The dielectric layer exposes a channel region of the first fin. A doping concentration at a lateral surface of the channel region and a doping concentration at a central region of the channel region are different from each other in the at least one second epitaxial layer. After the at least one first epitaxial layer is removed from the channel region, the at least one second epitaxial layer in the channel region serves as at least one nanowire. A gate surrounding the at least one nanowire is formed.