Self-Aligned Nanowire Formation via Double Patterning
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Solution Overview
Problem
The increasing down-scaling of integrated circuits poses challenges due to the optical proximity effect, where closely located features tend to short to each other, necessitating advanced patterning techniques to maintain feature density and prevent misalignment.
Innovation Solution
The implementation of a self-aligned nanowire formation method using double patterning technology, which involves multiple layers and etching processes to create semiconductor nanowires with precise alignment and reduced overlay misalignment risks, allowing for smaller feature sizes beyond traditional lithography limits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional single-mask lithography is used, then the manufacturing process is simple, but the optical proximity effect causes closely located features to short to each other
Solution Approach 1:
The patent divides the patterning process into two separate masks (first mask and second mask) in a double-patterning sequence. The first mask defines initial features, and the second mask defines additional features at different locations. This segmentation allows closely spaced features to be formed without optical proximity effects, as each mask only needs to resolve features at its own pitch, not the combined pitch of both masks.
2Productivity
If feature size is reduced below lithography limits, then higher feature density is achieved, but alignment precision deteriorates due to overlay misalignment
Solution Approach 1:
The patent employs self-aligned spacer formation where spacers are deposited conformally on mandrels and then etched back. The spacers automatically align to the mandrels through the conformal deposition process, eliminating the need for separate alignment steps. This self-alignment mechanism ensures precise positioning of features even at reduced dimensions, maintaining manufacturing precision while enabling higher feature density.
3Manufacturing precision
If double patterning is implemented to reduce optical proximity effect, then feature separation precision is improved, but device complexity increases
Solution Approach 1:
The patent transitions from planar 2D patterning to 3D structured patterning by forming vertical spacers and mandrels. The double-patterning process utilizes vertical dimension (thickness of spacers and mandrels) in addition to horizontal patterning. This dimensional transition allows the process to achieve precise feature separation while managing complexity through systematic 3D structure formation rather than purely 2D mask design.
Data Source
AI summary
A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.