Nanowire-Supported Electrode Pad Layout for Low-Noise Semiconductors
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Solution Overview
Problem
In semiconductor devices, particularly in quantum computers, the parasitic capacitance of the electrode pad acts as a major impediment to noise reduction due to its relatively large size compared to the gate length, limiting the effectiveness of low-noise amplifiers.
Innovation Solution
The semiconductor device incorporates nonconductive nanowires arranged perpendicularly on the substrate to support the electrode pad, creating a gap between the pad and the substrate, thereby reducing parasitic capacitance and enhancing noise reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the gate length is shortened to reduce intrinsic capacitance, then noise characteristics improve, but parasitic capacitance from the electrode pad remains large due to its minimum size requirements
Solution Approach 1:
The patent introduces nanowires extending in the vertical dimension to support the electrode pad, elevating it above the substrate surface. This dimensional transition creates spatial separation between the pad and substrate, reducing parasitic capacitance without requiring changes to the pad's horizontal area or the gate length.
Solution Approach 2:
The nanowires act as intermediary support structures between the electrode pad and the substrate. These nanowires provide mechanical support while electrically isolating the pad from the substrate, thereby reducing parasitic capacitance pathways while maintaining the necessary electrical connections.
2Object-affected harmful factors
If the electrode pad size is reduced to minimize parasitic capacitance, then noise reduction improves, but electrical connection reliability deteriorates due to minimum size requirements
Solution Approach 1:
By transitioning the support structure to the vertical dimension through nanowires, the patent maintains adequate pad area for reliable electrical connections while eliminating parasitic capacitance issues that would result from horizontal area reduction. The vertical support does not interfere with the pad's horizontal footprint.
Solution Approach 2:
The nanowire intermediary structures provide mechanical support and electrical isolation without compromising the electrode pad's area or connection reliability. The pad maintains its minimum required size for reliable connections while the nanowires prevent direct capacitive coupling to the substrate.
3Object-affected harmful factors
If the gate length is reduced to improve noise characteristics, then amplifier performance improves, but manufacturing precision requirements increase due to smaller dimensions
Solution Approach 1:
The patent extracts the parasitic capacitance problem from the gate structure by introducing nanowire-supported electrode pads. This separation allows the gate length to be optimized for intrinsic capacitance reduction without being constrained by pad-related parasitic effects, thereby reducing the impact of manufacturing precision variations on overall device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces the parasitic capacitance and noise in the signal input to the transistor, improving the noise figure and reducing the noise temperature, as demonstrated by the comparison between conventional and nanowire-supported pad configurations.
Implementation Method 1
an electrode pad formed at upper ends of the plurality of nanowires so as to have a gap between the electrode pad and the substrate, the electrode pad being supported by the plurality of nanowires
Data Source
AI summary
A semiconductor device includes a substrate; a gate electrode, a source electrode, and a drain electrode, the gate electrode, the source electrode and the drain electrode being formed on the substrate; a plurality of nonconductive nanowires formed two-dimensionally on an upper surface of the substrate so as to extend perpendicularly to the upper surface of the substrate; an electrode pad formed at upper ends of the plurality of nanowires so as to have a gap between the electrode pad and the substrate, the electrode pad being supported by the plurality of nanowires; and an extraction electrode connecting the electrode pad and the gate electrode.