Gate-All-Around Nanowire Layout for ESD Substrate Contact
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Solution Overview
Problem
The challenge in integrated circuit fabrication is the lack of electrical contact between nanowire or nanoribbon transistors and the underlying substrate, which leads to issues with charge dissipation during electrostatic discharge (ESD) events and thermal management, particularly in nanowire and nanoribbon architectures where traditional finFET-based solutions do not translate.
Innovation Solution
The approach involves retaining silicon germanium (SiGe) or silicon (Si) in the nanostack to form a channel-to-substrate electrical contact, allowing for proper charge dissipation and thermal management by inhibiting nanowire release during fabrication, enabling epitaxial growth for low resistance source or drain regions and enhancing heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If nanowire and nanoribbon transistor architectures are used to scale down device dimensions, then device density and short channel control are improved, but reliable electrical connection to substrate for charge dissipation is lost
Solution Approach 1:
The patent introduces an intermediary conductive structure (metal plug or doped region) between the nanowire/nanoribbon channel and the substrate to establish reliable electrical connection. This intermediary component bridges the gap between the suspended channel structure and the substrate, enabling charge dissipation while preserving the benefits of the scaled architecture.
Solution Approach 2:
The patent transitions from a planar contact geometry to a vertical or three-dimensional contact structure. By extending the contact structure vertically through the isolation layer to reach the substrate, the patent establishes electrical connection in a different spatial dimension, avoiding interference with the lateral scaling of the channel.
2Ease of manufacture
If conventional tri-gate transistor fabrication on bulk silicon is used, then manufacturing cost is reduced and process complexity is lowered, but mobility improvement and short channel control deteriorate at dimensions below 10 nm
Solution Approach 1:
The patent transitions from planar 2D channel structures to vertically stacked 3D nanowire or nanoribbon channels. This dimensional change provides gate-all-around control of the channel, significantly improving short channel control and carrier mobility while maintaining compatibility with bulk silicon substrates and conventional fabrication processes.
Solution Approach 2:
The patent employs composite material structures including alternating layers of channel material (e.g., Si/SiGe) to create suspended nanowire or nanoribbon structures. This composite approach enables precise control of electrical properties while maintaining mechanical support and thermal management, achieving superior device performance at scaled dimensions.
3Productivity
If feature size is reduced to increase device density, then capacity increases, but lithographic patterning constraints and spacing requirements become overwhelming
Solution Approach 1:
The patent moves critical device features from the lateral plane to the vertical dimension. By forming nanowire channels and gate structures vertically, the patent reduces the lateral footprint of each device, increasing density without proportionally increasing lithographic complexity. The vertical structures can be formed using self-aligned processes that are less constrained by lithographic resolution.
Solution Approach 2:
The patent divides the channel into multiple discrete nanowire segments stacked vertically, with each segment independently controlled by the gate. This segmentation allows for higher density packing while using standard lithographic features for the base structure, reducing the burden on lithographic precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution ensures robust functionality of nanowire and nanoribbon transistors during ESD events and thermal sensing applications by providing a reliable electrical path for charge dissipation and heat management, comparable to traditional bulk diode performance.
Implementation Method 1
retaining silicon germanium (SiGe) or silicon (Si) in the nanostack to form a channel-to-substrate electrical contact, allowing for proper charge dissipation
Implementation Method 2
enabling epitaxial growth for low resistance source or drain regions
Implementation Method 3
providing a reliable electrical path for charge dissipation and heat management, comparable to traditional bulk diode performance
Data Source
AI summary
Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A channel region of the first vertical arrangement of horizontal nanowires is electrically coupled to the first fin by a semiconductor material layer directly between the first vertical arrangement of horizontal nanowires and the first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A second vertical arrangement of horizontal nanowires is above a second fin. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires.